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Searched refs:mode_offset (Results 1 - 20 of 20) sorted by relevance

/kernel/linux/linux-6.6/arch/arm/mach-omap1/
H A Dmux.h27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
29 .mask_offset = mode_offset, \
41 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
43 .mask_offset = mode_offset, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
54 .mask_offset = mode_offset, \
64 #define MUX_REG_7XX(reg, mode_offset, mode) \
66 .mask_offset = mode_offset, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
81 MUX_REG(mux_reg, mode_offset, mod
[all...]
/kernel/linux/linux-5.10/arch/arm/mach-davinci/
H A Dmux.h18 #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
24 .mask_offset = mode_offset, \
29 #define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
35 .mask_offset = mode_offset, \
40 #define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
46 .mask_offset = mode_offset, \
/kernel/linux/linux-5.10/arch/arm/mach-omap1/include/mach/
H A Dmux.h27 #define MUX_REG(reg, mode_offset, mode) .mux_reg_name = "FUNC_MUX_CTRL_"#reg, \
29 .mask_offset = mode_offset, \
41 #define MUX_REG_7XX(reg, mode_offset, mode) .mux_reg_name = "OMAP7XX_IO_CONF_"#reg, \
43 .mask_offset = mode_offset, \
53 #define MUX_REG(reg, mode_offset, mode) .mux_reg = FUNC_MUX_CTRL_##reg, \
54 .mask_offset = mode_offset, \
64 #define MUX_REG_7XX(reg, mode_offset, mode) \
66 .mask_offset = mode_offset, \
75 #define MUX_CFG(desc, mux_reg, mode_offset, mode, \
81 MUX_REG(mux_reg, mode_offset, mod
[all...]
/kernel/linux/linux-5.10/drivers/media/cec/core/
H A Dcec-pin-error-inj.c14 unsigned int mode_offset; member
195 unsigned int mode_offset; in cec_pin_error_inj_parse_line() local
203 mode_offset = cec_error_inj_cmds[i].mode_offset; in cec_pin_error_inj_parse_line()
204 mode_mask = CEC_ERROR_INJ_MODE_MASK << mode_offset; in cec_pin_error_inj_parse_line()
207 if (mode_offset == CEC_ERROR_INJ_RX_ARB_LOST_OFFSET) { in cec_pin_error_inj_parse_line()
213 } else if (mode_offset == CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET) { in cec_pin_error_inj_parse_line()
225 if ((mode_offset == CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET || in cec_pin_error_inj_parse_line()
226 mode_offset == CEC_ERROR_INJ_TX_LONG_BIT_OFFSET || in cec_pin_error_inj_parse_line()
227 mode_offset in cec_pin_error_inj_parse_line()
317 unsigned int mode_offset; cec_pin_error_inj_show() local
[all...]
H A Dcec-pin.c156 static bool rx_error_inj(struct cec_pin *pin, unsigned int mode_offset, in rx_error_inj() argument
162 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; in rx_error_inj()
176 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); in rx_error_inj()
218 static bool tx_error_inj(struct cec_pin *pin, unsigned int mode_offset, in tx_error_inj() argument
224 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; in tx_error_inj()
238 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); in tx_error_inj()
/kernel/linux/linux-6.6/drivers/media/cec/core/
H A Dcec-pin-error-inj.c14 unsigned int mode_offset; member
195 unsigned int mode_offset; in cec_pin_error_inj_parse_line() local
203 mode_offset = cec_error_inj_cmds[i].mode_offset; in cec_pin_error_inj_parse_line()
204 mode_mask = CEC_ERROR_INJ_MODE_MASK << mode_offset; in cec_pin_error_inj_parse_line()
207 if (mode_offset == CEC_ERROR_INJ_RX_ARB_LOST_OFFSET) { in cec_pin_error_inj_parse_line()
213 } else if (mode_offset == CEC_ERROR_INJ_TX_ADD_BYTES_OFFSET) { in cec_pin_error_inj_parse_line()
225 if ((mode_offset == CEC_ERROR_INJ_TX_SHORT_BIT_OFFSET || in cec_pin_error_inj_parse_line()
226 mode_offset == CEC_ERROR_INJ_TX_LONG_BIT_OFFSET || in cec_pin_error_inj_parse_line()
227 mode_offset in cec_pin_error_inj_parse_line()
317 unsigned int mode_offset; cec_pin_error_inj_show() local
[all...]
H A Dcec-pin.c156 static bool rx_error_inj(struct cec_pin *pin, unsigned int mode_offset, in rx_error_inj() argument
162 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; in rx_error_inj()
176 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); in rx_error_inj()
218 static bool tx_error_inj(struct cec_pin *pin, unsigned int mode_offset, in tx_error_inj() argument
224 unsigned int mode = (e >> mode_offset) & CEC_ERROR_INJ_MODE_MASK; in tx_error_inj()
238 ~(CEC_ERROR_INJ_MODE_MASK << mode_offset); in tx_error_inj()
/kernel/linux/linux-6.6/arch/arm/mach-davinci/
H A Dmux.h668 #define MUX_CFG(soc, desc, muxreg, mode_offset, mode_mask, mux_mode, dbg)\
674 .mask_offset = mode_offset, \
679 #define INT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
685 .mask_offset = mode_offset, \
690 #define EVT_CFG(soc, desc, mode_offset, mode_mask, mux_mode, dbg) \
696 .mask_offset = mode_offset, \
/kernel/linux/linux-5.10/include/linux/
H A Dpktcdvd.h174 __u8 mode_offset; /* 0 / 8 */ member
/kernel/linux/linux-6.6/include/linux/
H A Dpktcdvd.h165 __u8 mode_offset; /* 0 / 8 */ member
/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk.h267 * @mode_offset: offset of the register for configuring the PLL-mode.
285 int mode_offset; member
305 .mode_offset = _mode, \
316 int lock_shift, int mode_offset, int mode_shift,
H A Dclk-pll.c853 int lock_shift, int mode_offset, int mode_shift, in rockchip_clk_register_pll()
880 pll_mux->reg = ctx->reg_base + mode_offset; in rockchip_clk_register_pll()
849 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
H A Dclk.c427 list->lock_shift, list->mode_offset, in rockchip_clk_register_plls()
/kernel/linux/linux-5.10/drivers/block/
H A Dpktcdvd.c1610 pd->mode_offset = (buffer[6] << 8) | (buffer[7] & 0xff); in pkt_set_write_settings()
1628 wp = (write_param_page *) &buffer[sizeof(struct mode_page_header) + pd->mode_offset]; in pkt_set_write_settings()
1862 cgc.buflen = pd->mode_offset + 12; in pkt_write_caching()
1873 buf[pd->mode_offset + 10] |= (!!set << 2); in pkt_write_caching()
1907 cap_buf = &buf[sizeof(struct mode_page_header) + pd->mode_offset]; in pkt_get_max_speed()
1913 cgc.buflen = pd->mode_offset + cap_buf[1] + 2 + in pkt_get_max_speed()
2485 seq_printf(m, "\tmode page offset:\t%u\n", pd->mode_offset); in pkt_seq_show()
/kernel/linux/linux-6.6/drivers/block/
H A Dpktcdvd.c477 seq_printf(m, "\tmode page offset:\t%u\n", pd->mode_offset); in pkt_seq_show()
1647 pd->mode_offset = get_unaligned_be16(&buffer[6]); in pkt_set_write_settings()
1665 wp = (write_param_page *) &buffer[sizeof(struct mode_page_header) + pd->mode_offset]; in pkt_set_write_settings()
1904 cgc.buflen = pd->mode_offset + 12; in pkt_write_caching()
1920 buf[pd->mode_offset + 10] |= (set << 2); in pkt_write_caching()
1954 cap_buf = &buf[sizeof(struct mode_page_header) + pd->mode_offset]; in pkt_get_max_speed()
1960 cgc.buflen = pd->mode_offset + cap_buf[1] + 2 + in pkt_get_max_speed()
/kernel/linux/linux-5.10/drivers/net/wireless/ath/ath5k/
H A Deeprom.c470 u32 mode_offset[3]; in ath5k_eeprom_init_modes() local
478 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); in ath5k_eeprom_init_modes()
479 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); in ath5k_eeprom_init_modes()
480 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); in ath5k_eeprom_init_modes()
486 offset = mode_offset[mode]; in ath5k_eeprom_init_modes()
/kernel/linux/linux-6.6/drivers/net/wireless/ath/ath5k/
H A Deeprom.c470 u32 mode_offset[3]; in ath5k_eeprom_init_modes() local
478 mode_offset[AR5K_EEPROM_MODE_11A] = AR5K_EEPROM_MODES_11A(ah->ah_ee_version); in ath5k_eeprom_init_modes()
479 mode_offset[AR5K_EEPROM_MODE_11B] = AR5K_EEPROM_MODES_11B(ah->ah_ee_version); in ath5k_eeprom_init_modes()
480 mode_offset[AR5K_EEPROM_MODE_11G] = AR5K_EEPROM_MODES_11G(ah->ah_ee_version); in ath5k_eeprom_init_modes()
486 offset = mode_offset[mode]; in ath5k_eeprom_init_modes()
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk.h384 * @mode_offset: offset of the register for configuring the PLL-mode.
402 int mode_offset; member
422 .mode_offset = _mode, \
433 int lock_shift, int mode_offset, int mode_shift,
H A Dclk-pll.c1060 int lock_shift, int mode_offset, int mode_shift, in rockchip_clk_register_pll()
1087 pll_mux->reg = ctx->reg_base + mode_offset; in rockchip_clk_register_pll()
1056 rockchip_clk_register_pll(struct rockchip_clk_provider *ctx, enum rockchip_pll_type pll_type, const char *name, const char *const *parent_names, u8 num_parents, int con_offset, int grf_lock_offset, int lock_shift, int mode_offset, int mode_shift, struct rockchip_pll_rate_table *rate_table, unsigned long flags, u8 clk_pll_flags) rockchip_clk_register_pll() argument
H A Dclk.c418 list->lock_shift, list->mode_offset, in rockchip_clk_register_plls()

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