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Help
Searched
refs:mg_pll_bias
(Results
1 - 8
of
8
) sorted by relevance
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H
A
D
intel_dpll_mgr.h
221
u32
mg_pll_bias
;
member
H
A
D
intel_dpll_mgr.c
2979
pll_state->
mg_pll_bias
= (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
in icl_calc_mg_pll_state()
3030
pll_state->
mg_pll_bias
=
in icl_calc_mg_pll_state()
3050
pll_state->
mg_pll_bias
&= pll_state->mg_pll_bias_mask;
in icl_calc_mg_pll_state()
3070
if (pll_state->
mg_pll_bias
& DKL_PLL_BIAS_FRAC_EN_H) {
in icl_ddi_mg_pll_get_freq()
3071
m2_frac = pll_state->
mg_pll_bias
&
in icl_ddi_mg_pll_get_freq()
3441
hw_state->
mg_pll_bias
= intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
in mg_pll_get_hw_state()
3454
hw_state->
mg_pll_bias
&= hw_state->mg_pll_bias_mask;
in mg_pll_get_hw_state()
3518
hw_state->
mg_pll_bias
= intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
in dkl_pll_get_hw_state()
3519
hw_state->
mg_pll_bias
&= (DKL_PLL_BIAS_FRAC_EN_H |
in dkl_pll_get_hw_state()
3685
hw_state->mg_pll_bias_mask, hw_state->
mg_pll_bias
);
in icl_mg_pll_write()
[all...]
H
A
D
intel_display_debugfs.c
686
seq_printf(m, "
mg_pll_bias
: 0x%08x\n",
in i915_shared_dplls_info()
687
pll->state.hw_state.
mg_pll_bias
);
in i915_shared_dplls_info()
H
A
D
intel_display.c
5346
PIPE_CONF_CHECK_X(dpll_hw_state.
mg_pll_bias
);
in intel_pipe_config_compare()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H
A
D
intel_dpll_mgr.h
209
u32
mg_pll_bias
;
member
H
A
D
intel_dpll_mgr.c
3311
pll_state->
mg_pll_bias
= (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
in icl_calc_mg_pll_state()
3362
pll_state->
mg_pll_bias
=
in icl_calc_mg_pll_state()
3382
pll_state->
mg_pll_bias
&= pll_state->mg_pll_bias_mask;
in icl_calc_mg_pll_state()
3402
if (pll_state->
mg_pll_bias
& DKL_PLL_BIAS_FRAC_EN_H) {
in icl_ddi_mg_pll_get_freq()
3403
m2_frac = pll_state->
mg_pll_bias
&
in icl_ddi_mg_pll_get_freq()
3718
hw_state->
mg_pll_bias
= intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
in mg_pll_get_hw_state()
3731
hw_state->
mg_pll_bias
&= hw_state->mg_pll_bias_mask;
in mg_pll_get_hw_state()
3798
hw_state->
mg_pll_bias
= intel_de_read(dev_priv, DKL_PLL_BIAS(tc_port));
in dkl_pll_get_hw_state()
3799
hw_state->
mg_pll_bias
&= (DKL_PLL_BIAS_FRAC_EN_H |
in dkl_pll_get_hw_state()
3946
val |= hw_state->
mg_pll_bias
;
in icl_mg_pll_write()
[all...]
H
A
D
intel_display_debugfs.c
960
seq_printf(m, "
mg_pll_bias
: 0x%08x\n",
in i915_shared_dplls_info()
961
pll->state.hw_state.
mg_pll_bias
);
in i915_shared_dplls_info()
H
A
D
intel_display.c
14018
PIPE_CONF_CHECK_X(dpll_hw_state.
mg_pll_bias
);
in intel_pipe_config_compare()
Completed in 48 milliseconds