Home
last modified time | relevance | path

Searched refs:mg_clktop2_hsclkctl (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h215 u32 mg_clktop2_hsclkctl; member
H A Dintel_dpll_mgr.c2836 state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
3090 switch (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3105 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3109 div2 = (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3426 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3428 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3489 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3491 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3675 hw_state->mg_clktop2_hsclkctl); in icl_mg_pll_write()
3721 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
[all...]
H A Dintel_display_debugfs.c674 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", in i915_shared_dplls_info()
675 pll->state.hw_state.mg_clktop2_hsclkctl); in i915_shared_dplls_info()
H A Dintel_display.c5340 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); in intel_pipe_config_compare()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dpll_mgr.h203 u32 mg_clktop2_hsclkctl; member
H A Dintel_dpll_mgr.c3166 state->mg_clktop2_hsclkctl = in icl_mg_pll_find_divisors()
3422 switch (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3437 MISSING_CASE(pll_state->mg_clktop2_hsclkctl); in icl_ddi_mg_pll_get_freq()
3441 div2 = (pll_state->mg_clktop2_hsclkctl & in icl_ddi_mg_pll_get_freq()
3703 hw_state->mg_clktop2_hsclkctl = in mg_pll_get_hw_state()
3705 hw_state->mg_clktop2_hsclkctl &= in mg_pll_get_hw_state()
3769 hw_state->mg_clktop2_hsclkctl = in dkl_pll_get_hw_state()
3771 hw_state->mg_clktop2_hsclkctl &= in dkl_pll_get_hw_state()
3934 val |= hw_state->mg_clktop2_hsclkctl; in icl_mg_pll_write()
3987 val |= hw_state->mg_clktop2_hsclkctl; in dkl_pll_write()
[all...]
H A Dintel_display_debugfs.c948 seq_printf(m, " mg_clktop2_hsclkctl: 0x%08x\n", in i915_shared_dplls_info()
949 pll->state.hw_state.mg_clktop2_hsclkctl); in i915_shared_dplls_info()
H A Dintel_display.c14012 PIPE_CONF_CHECK_X(dpll_hw_state.mg_clktop2_hsclkctl); in intel_pipe_config_compare()

Completed in 50 milliseconds