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Searched refs:mdiv (Results 1 - 25 of 67) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/clk/bcm/
H A Dclk-ns2.c62 .mdiv = REG_VAL(0x18, 0, 8),
68 .mdiv = REG_VAL(0x18, 8, 8),
74 .mdiv = REG_VAL(0x14, 0, 8),
80 .mdiv = REG_VAL(0x14, 8, 8),
86 .mdiv = REG_VAL(0x14, 16, 8),
92 .mdiv = REG_VAL(0x14, 24, 8),
124 .mdiv = REG_VAL(0x18, 0, 8),
130 .mdiv = REG_VAL(0x18, 8, 8),
136 .mdiv = REG_VAL(0x14, 0, 8),
142 .mdiv
[all...]
H A Dclk-sr.c52 .mdiv = REG_VAL(0x18, 0, 9),
58 .mdiv = REG_VAL(0x18, 10, 9),
64 .mdiv = REG_VAL(0x18, 20, 9),
70 .mdiv = REG_VAL(0x1c, 0, 9),
76 .mdiv = REG_VAL(0x1c, 10, 9),
82 .mdiv = REG_VAL(0x1c, 20, 9),
112 .mdiv = REG_VAL(0x18, 0, 9),
118 .mdiv = REG_VAL(0x18, 10, 9),
124 .mdiv = REG_VAL(0x18, 20, 9),
130 .mdiv
[all...]
H A Dclk-cygnus.c76 .mdiv = REG_VAL(0x20, 0, 8),
82 .mdiv = REG_VAL(0x20, 10, 8),
88 .mdiv = REG_VAL(0x20, 20, 8),
94 .mdiv = REG_VAL(0x24, 0, 8),
100 .mdiv = REG_VAL(0x24, 10, 8),
106 .mdiv = REG_VAL(0x24, 20, 8),
134 .mdiv = REG_VAL(0x8, 0, 8),
140 .mdiv = REG_VAL(0x8, 10, 8),
146 .mdiv = REG_VAL(0x8, 20, 8),
152 .mdiv
[all...]
H A Dclk-iproc-armpll.c109 * Determine the mdiv (post divider) based on the frequency ID being used.
119 int mdiv; in __get_mdiv() local
127 mdiv = 1; in __get_mdiv()
132 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; in __get_mdiv()
133 if (mdiv == 0) in __get_mdiv()
134 mdiv = 256; in __get_mdiv()
139 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; in __get_mdiv()
140 if (mdiv == 0) in __get_mdiv()
141 mdiv = 256; in __get_mdiv()
145 mdiv in __get_mdiv()
200 int mdiv; iproc_arm_pll_recalc_rate() local
[all...]
H A Dclk-nsp.c61 .mdiv = REG_VAL(0x18, 16, 8),
67 .mdiv = REG_VAL(0x18, 8, 8),
73 .mdiv = REG_VAL(0x18, 0, 8),
79 .mdiv = REG_VAL(0x1c, 16, 8),
85 .mdiv = REG_VAL(0x1c, 8, 8),
91 .mdiv = REG_VAL(0x1c, 0, 8),
118 .mdiv = REG_VAL(0x8, 24, 8),
124 .mdiv = REG_VAL(0x8, 16, 8),
130 .mdiv = REG_VAL(0x8, 8, 8),
H A Dclk-iproc-pll.c627 unsigned int mdiv; in iproc_clk_recalc_rate() local
633 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
634 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
635 if (mdiv == 0) in iproc_clk_recalc_rate()
636 mdiv = 256; in iproc_clk_recalc_rate()
639 rate = parent_rate / (mdiv * 2); in iproc_clk_recalc_rate()
641 rate = parent_rate / mdiv; in iproc_clk_recalc_rate()
687 val = readl(pll->control_base + ctrl->mdiv in iproc_clk_set_rate()
[all...]
/kernel/linux/linux-6.6/drivers/clk/bcm/
H A Dclk-ns2.c52 .mdiv = REG_VAL(0x18, 0, 8),
58 .mdiv = REG_VAL(0x18, 8, 8),
64 .mdiv = REG_VAL(0x14, 0, 8),
70 .mdiv = REG_VAL(0x14, 8, 8),
76 .mdiv = REG_VAL(0x14, 16, 8),
82 .mdiv = REG_VAL(0x14, 24, 8),
114 .mdiv = REG_VAL(0x18, 0, 8),
120 .mdiv = REG_VAL(0x18, 8, 8),
126 .mdiv = REG_VAL(0x14, 0, 8),
132 .mdiv
[all...]
H A Dclk-sr.c52 .mdiv = REG_VAL(0x18, 0, 9),
58 .mdiv = REG_VAL(0x18, 10, 9),
64 .mdiv = REG_VAL(0x18, 20, 9),
70 .mdiv = REG_VAL(0x1c, 0, 9),
76 .mdiv = REG_VAL(0x1c, 10, 9),
82 .mdiv = REG_VAL(0x1c, 20, 9),
112 .mdiv = REG_VAL(0x18, 0, 9),
118 .mdiv = REG_VAL(0x18, 10, 9),
124 .mdiv = REG_VAL(0x18, 20, 9),
130 .mdiv
[all...]
H A Dclk-cygnus.c66 .mdiv = REG_VAL(0x20, 0, 8),
72 .mdiv = REG_VAL(0x20, 10, 8),
78 .mdiv = REG_VAL(0x20, 20, 8),
84 .mdiv = REG_VAL(0x24, 0, 8),
90 .mdiv = REG_VAL(0x24, 10, 8),
96 .mdiv = REG_VAL(0x24, 20, 8),
124 .mdiv = REG_VAL(0x8, 0, 8),
130 .mdiv = REG_VAL(0x8, 10, 8),
136 .mdiv = REG_VAL(0x8, 20, 8),
142 .mdiv
[all...]
H A Dclk-iproc-armpll.c99 * Determine the mdiv (post divider) based on the frequency ID being used.
109 int mdiv; in __get_mdiv() local
117 mdiv = 1; in __get_mdiv()
122 mdiv = val & IPROC_CLK_PLLARMC_MDIV_MASK; in __get_mdiv()
123 if (mdiv == 0) in __get_mdiv()
124 mdiv = 256; in __get_mdiv()
129 mdiv = val & IPROC_CLK_PLLARMCTL5_H_MDIV_MASK; in __get_mdiv()
130 if (mdiv == 0) in __get_mdiv()
131 mdiv = 256; in __get_mdiv()
135 mdiv in __get_mdiv()
190 int mdiv; iproc_arm_pll_recalc_rate() local
[all...]
H A Dclk-nsp.c51 .mdiv = REG_VAL(0x18, 16, 8),
57 .mdiv = REG_VAL(0x18, 8, 8),
63 .mdiv = REG_VAL(0x18, 0, 8),
69 .mdiv = REG_VAL(0x1c, 16, 8),
75 .mdiv = REG_VAL(0x1c, 8, 8),
81 .mdiv = REG_VAL(0x1c, 0, 8),
108 .mdiv = REG_VAL(0x8, 24, 8),
114 .mdiv = REG_VAL(0x8, 16, 8),
120 .mdiv = REG_VAL(0x8, 8, 8),
H A Dclk-iproc-pll.c617 unsigned int mdiv; in iproc_clk_recalc_rate() local
623 val = readl(pll->control_base + ctrl->mdiv.offset); in iproc_clk_recalc_rate()
624 mdiv = (val >> ctrl->mdiv.shift) & bit_mask(ctrl->mdiv.width); in iproc_clk_recalc_rate()
625 if (mdiv == 0) in iproc_clk_recalc_rate()
626 mdiv = 256; in iproc_clk_recalc_rate()
629 rate = parent_rate / (mdiv * 2); in iproc_clk_recalc_rate()
631 rate = parent_rate / mdiv; in iproc_clk_recalc_rate()
677 val = readl(pll->control_base + ctrl->mdiv in iproc_clk_set_rate()
[all...]
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-pll14xx.c104 static long pll14xx_calc_rate(struct clk_pll14xx *pll, int mdiv, int pdiv, in pll14xx_calc_rate() argument
110 fvco *= (mdiv * 65536 + kdiv); in pll14xx_calc_rate()
118 static long pll1443x_calc_kdiv(int mdiv, int pdiv, int sdiv, in pll1443x_calc_kdiv() argument
123 /* calc kdiv = round(rate * pdiv * 65536 * 2^sdiv / prate) - (mdiv * 65536) */ in pll1443x_calc_kdiv()
124 kdiv = ((rate * ((pdiv * 65536) << sdiv) + prate / 2) / prate) - (mdiv * 65536); in pll1443x_calc_kdiv()
133 int mdiv, pdiv, sdiv, kdiv; in imx_pll14xx_calc_settings() local
154 t->mdiv = tt->mdiv; in imx_pll14xx_calc_settings()
162 mdiv = FIELD_GET(MDIV_MASK, pll_div_ctl0); in imx_pll14xx_calc_settings()
168 rate_min = pll14xx_calc_rate(pll, mdiv, pdi in imx_pll14xx_calc_settings()
247 u32 mdiv, pdiv, sdiv, kdiv, pll_div_ctl0, pll_div_ctl1; clk_pll14xx_recalc_rate() local
[all...]
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-pll.c153 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
157 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
161 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
186 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
190 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
194 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
223 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
227 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
231 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
245 return (rate->mdiv ! in samsung_pll35xx_mp_change()
327 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll36xx_recalc_rate() local
437 u32 mdiv, pdiv, sdiv, pll_con3; samsung_pll0822x_recalc_rate() local
522 u32 mdiv, pdiv, sdiv, pll_con3, pll_con5; samsung_pll0831x_recalc_rate() local
620 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll45xx_recalc_rate() local
753 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; samsung_pll46xx_recalc_rate() local
882 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll6552_recalc_rate() local
922 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; samsung_pll6553_recalc_rate() local
1001 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll2550xx_recalc_rate() local
1015 samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) samsung_pll2550xx_mp_change() argument
1102 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll2650x_recalc_rate() local
1193 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; samsung_pll2650xx_recalc_rate() local
[all...]
H A Dclk-pll.h52 .mdiv = (_m), \
61 .mdiv = (_m), \
71 .mdiv = (_m), \
81 .mdiv = (_m), \
92 .mdiv = (_m), \
106 unsigned int mdiv; member
/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-pll.c109 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll2126_recalc_rate() local
113 mdiv = (pll_con >> PLL2126_MDIV_SHIFT) & PLL2126_MDIV_MASK; in samsung_pll2126_recalc_rate()
117 fvco *= (mdiv + 8); in samsung_pll2126_recalc_rate()
142 u32 pll_con, mdiv, pdiv, sdiv; in samsung_pll3000_recalc_rate() local
146 mdiv = (pll_con >> PLL3000_MDIV_SHIFT) & PLL3000_MDIV_MASK; in samsung_pll3000_recalc_rate()
150 fvco *= (2 * (mdiv + 8)); in samsung_pll3000_recalc_rate()
179 u32 mdiv, pdiv, sdiv, pll_con; in samsung_pll35xx_recalc_rate() local
183 mdiv = (pll_con >> PLL35XX_MDIV_SHIFT) & PLL35XX_MDIV_MASK; in samsung_pll35xx_recalc_rate()
187 fvco *= mdiv; in samsung_pll35xx_recalc_rate()
201 return (rate->mdiv ! in samsung_pll35xx_mp_change()
286 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll36xx_recalc_rate() local
404 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll45xx_recalc_rate() local
551 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1, shift; samsung_pll46xx_recalc_rate() local
694 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll6552_recalc_rate() local
734 u32 mdiv, pdiv, sdiv, kdiv, pll_con0, pll_con1; samsung_pll6553_recalc_rate() local
772 u32 pll_con, mdiv, pdiv, sdiv; samsung_s3c2410_pll_recalc_rate() local
790 u32 pll_con, mdiv, pdiv, sdiv; samsung_s3c2440_mpll_recalc_rate() local
976 u32 mdiv, pdiv, sdiv, pll_con; samsung_pll2550xx_recalc_rate() local
990 samsung_pll2550xx_mp_change(u32 mdiv, u32 pdiv, u32 pll_con) samsung_pll2550xx_mp_change() argument
1082 u32 mdiv, pdiv, sdiv, pll_con0, pll_con1; samsung_pll2650x_recalc_rate() local
1177 u32 mdiv, pdiv, sdiv, pll_con0, pll_con2; samsung_pll2650xx_recalc_rate() local
[all...]
H A Dclk-pll.h50 .mdiv = (_m), \
59 .mdiv = (_m), \
68 .mdiv = (_m), \
77 .mdiv = (_m), \
87 .mdiv = (_m), \
97 .mdiv = (_m), \
108 .mdiv = (_m), \
122 unsigned int mdiv; member
/kernel/linux/linux-5.10/arch/arm/mach-s3c/
H A Dregs-s3c2443-clock.h153 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_mpll() local
156 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_mpll()
160 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_mpll()
164 fvco = (uint64_t)baseclk * (2 * (mdiv + 8)); in s3c2443_get_mpll()
173 unsigned int mdiv, pdiv, sdiv; in s3c2443_get_epll() local
176 mdiv = pllval >> S3C2443_PLLCON_MDIVSHIFT; in s3c2443_get_epll()
180 mdiv &= S3C2443_PLLCON_MDIVMASK; in s3c2443_get_epll()
184 fvco = (uint64_t)baseclk * (mdiv + 8); in s3c2443_get_epll()
/kernel/linux/linux-5.10/drivers/clk/socfpga/
H A Dclk-pll-s10.c38 unsigned long arefdiv, reg, mdiv; in agilex_clk_pll_recalc_rate() local
47 /* Read mdiv and fdiv from the fdbck register */ in agilex_clk_pll_recalc_rate()
49 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; in agilex_clk_pll_recalc_rate()
51 vco_freq = (unsigned long long)vco_freq * mdiv; in agilex_clk_pll_recalc_rate()
59 unsigned long mdiv; in clk_pll_recalc_rate() local
71 /* Read mdiv and fdiv from the fdbck register */ in clk_pll_recalc_rate()
73 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; in clk_pll_recalc_rate()
74 vco_freq = (unsigned long long)vco_freq * (mdiv + 6); in clk_pll_recalc_rate()
/kernel/linux/linux-5.10/drivers/clk/st/
H A Dclkgen-fsyn.c35 unsigned long mdiv; member
58 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member
92 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
143 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
492 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
577 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
601 fs_tmp.mdiv = (unsigned long) m; in clk_fs660c32_get_pe()
611 fs->mdiv = m; in clk_fs660c32_get_pe()
657 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
[all...]
/kernel/linux/linux-6.6/drivers/clk/st/
H A Dclkgen-fsyn.c35 unsigned long mdiv; member
58 struct clkgen_field mdiv[QUADFS_MAX_CHAN]; member
102 .mdiv = { CLKGEN_FIELD(0x304, 0x1f, 15),
165 .mdiv = { CLKGEN_FIELD(0x2b4, 0x1f, 15),
554 CLKGEN_WRITE(fs, mdiv[fs->chan], fs->md); in quadfs_fsynth_program_rate()
639 res = (P20 * (32 + fs->mdiv) + 32 * fs->pe) * s * ns; in clk_fs660c32_dig_get_rate()
663 fs_tmp.mdiv = (unsigned long) m; in clk_fs660c32_get_pe()
673 fs->mdiv = m; in clk_fs660c32_get_pe()
719 fs_tmp.mdiv = fs->mdiv; in clk_fs660c32_dig_get_params()
[all...]
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-pll14xx.c122 u32 mdiv, pdiv, sdiv, pll_div; in clk_pll1416x_recalc_rate() local
126 mdiv = (pll_div & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1416x_recalc_rate()
130 fvco *= mdiv; in clk_pll1416x_recalc_rate()
140 u32 mdiv, pdiv, sdiv, pll_div_ctl0, pll_div_ctl1; in clk_pll1443x_recalc_rate() local
146 mdiv = (pll_div_ctl0 & MDIV_MASK) >> MDIV_SHIFT; in clk_pll1443x_recalc_rate()
152 fvco *= (mdiv * 65536 + kdiv); in clk_pll1443x_recalc_rate()
168 return rate->mdiv != old_mdiv || rate->pdiv != old_pdiv; in clk_pll14xx_mp_change()
217 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1416x_set_rate()
282 div_val = (rate->mdiv << MDIV_SHIFT) | (rate->pdiv << PDIV_SHIFT) | in clk_pll1443x_set_rate()
/kernel/linux/linux-6.6/drivers/clk/socfpga/
H A Dclk-pll-s10.c65 unsigned long arefdiv, reg, mdiv; in agilex_clk_pll_recalc_rate() local
74 /* Read mdiv and fdiv from the fdbck register */ in agilex_clk_pll_recalc_rate()
76 mdiv = reg & SOCFPGA_AGILEX_PLL_MDIV_MASK; in agilex_clk_pll_recalc_rate()
78 vco_freq = (unsigned long long)vco_freq * mdiv; in agilex_clk_pll_recalc_rate()
86 unsigned long mdiv; in clk_pll_recalc_rate() local
98 /* Read mdiv and fdiv from the fdbck register */ in clk_pll_recalc_rate()
100 mdiv = (reg & SOCFPGA_PLL_MDIV_MASK) >> SOCFPGA_PLL_MDIV_SHIFT; in clk_pll_recalc_rate()
101 vco_freq = (unsigned long long)vco_freq * (mdiv + 6); in clk_pll_recalc_rate()
/kernel/linux/linux-5.10/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c35 u32 mdiv; member
320 info->mdiv |= 0x80000000; in calc_clk()
321 info->mdiv |= div1D; in calc_clk()
327 info->mdiv |= 0x80000000; in calc_clk()
328 info->mdiv |= div1P << 8; in calc_clk()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()
/kernel/linux/linux-6.6/drivers/gpu/drm/nouveau/nvkm/subdev/clk/
H A Dgk104.c35 u32 mdiv; member
320 info->mdiv |= 0x80000000; in calc_clk()
321 info->mdiv |= div1D; in calc_clk()
327 info->mdiv |= 0x80000000; in calc_clk()
328 info->mdiv |= div1P << 8; in calc_clk()
416 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x00003f00, info->mdiv); in gk104_clk_prog_3()
418 nvkm_mask(device, 0x137250 + (idx * 0x04), 0x0000003f, info->mdiv); in gk104_clk_prog_3()

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