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Searched refs:lane_count (Results 1 - 25 of 123) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/protocols/
H A Dlink_dp_training_fixed_vs_pe_retimer.c75 uint8_t lane_count) in dp_fixed_vs_pe_set_retimer_lane_settings()
82 for (lane = 0; lane < lane_count; lane++) { in dp_fixed_vs_pe_set_retimer_lane_settings()
252 lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy()
291 lt_settings->link_settings.lane_count, in dp_perform_fixed_vs_pe_training_sequence_legacy()
296 if (lt_settings->link_settings.lane_count == LANE_COUNT_FOUR) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
317 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dp_perform_fixed_vs_pe_training_sequence_legacy() local
368 for (lane = 0; lane < lane_count; lane++) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
406 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dp_perform_fixed_vs_pe_training_sequence_legacy()
439 status = dp_get_cr_failure(lane_count, dpcd_lane_statu in dp_perform_fixed_vs_pe_training_sequence_legacy()
72 dp_fixed_vs_pe_set_retimer_lane_settings( struct dc_link *link, const union dpcd_training_lane dpcd_lane_adjust[LANE_COUNT_DP_MAX], uint8_t lane_count) dp_fixed_vs_pe_set_retimer_lane_settings() argument
447 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; dp_perform_fixed_vs_pe_training_sequence_legacy() local
663 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; dp_perform_fixed_vs_pe_training_sequence() local
793 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; dp_perform_fixed_vs_pe_training_sequence() local
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H A Dlink_dp_capability.c66 enum dc_lane_count lane_count; member
101 .lane_count = LANE_COUNT_ONE,
425 static inline bool reached_minimum_lane_count(enum dc_lane_count lane_count) in reached_minimum_lane_count() argument
427 return lane_count <= LANE_COUNT_ONE; in reached_minimum_lane_count()
435 static enum dc_lane_count reduce_lane_count(enum dc_lane_count lane_count) in reduce_lane_count() argument
437 switch (lane_count) { in reduce_lane_count()
484 static enum dc_lane_count increase_lane_count(enum dc_lane_count lane_count) in increase_lane_count() argument
486 switch (lane_count) { in increase_lane_count()
539 if (dp_lt_fallbacks[cur_idx].lane_count == cur->lane_count in decide_fallback_link_setting_max_bw_policy()
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H A Dlink_dp_training_8b_10b.c103 lt_settings->link_settings.lane_count = link_setting->lane_count; in decide_8b_10b_training_settings()
163 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_clock_recovery_sequence() local
228 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in perform_8b_10b_clock_recovery_sequence()
267 return dp_get_cr_failure(lane_count, dpcd_lane_status); in perform_8b_10b_clock_recovery_sequence()
279 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in perform_8b_10b_channel_equalization_sequence() local
334 if (!dp_is_cr_done(lane_count, dpcd_lane_status)) in perform_8b_10b_channel_equalization_sequence()
340 if (dp_is_ch_eq_done(lane_count, dpcd_lane_statu in perform_8b_10b_channel_equalization_sequence()
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H A Dlink_dp_training_dpia.c298 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_non_transparent() local
403 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_non_transparent()
409 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_non_transparent()
468 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_cr_transparent() local
511 if (dp_is_cr_done(lane_count, dpcd_lane_status)) { in dpia_training_cr_transparent()
517 result = dp_get_cr_failure(lane_count, dpcd_lane_status); in dpia_training_cr_transparent()
623 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; in dpia_training_eq_non_transparent() local
771 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; dpia_training_eq_transparent() local
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H A Dlink_dp_training.c172 lt_settings->link_settings.lane_count, in dp_log_training_result()
313 for (lane = 1; lane < lt_settings->link_settings.lane_count; lane++) { in maximize_lane_settings()
463 (uint32_t)(lt_settings->link_settings.lane_count); in dp_is_max_vs_reached()
531 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_check_link_loss_status()
592 (uint32_t)(link_training_setting->link_settings.lane_count); in dp_get_lane_status_and_lane_adjust()
1048 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
1094 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1104 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
1129 link_training_setting->link_settings.lane_count); in dpcd_set_lane_settings()
1198 size_in_bytes = lt_settings->link_settings.lane_count * in dpcd_set_lt_pattern_and_lane_settings()
1348 enum dc_lane_count lane_count = perform_post_lt_adj_req_sequence() local
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H A Dlink_dp_irq_handler.c57 if (link->cur_link_settings.lane_count == 0) in dp_parse_link_loss_status()
63 for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) { in dp_parse_link_loss_status()
262 pipes[i]->link_config.dp_link_settings.lane_count = in dp_handle_link_loss()
263 link->verified_link_cap.lane_count; in dp_handle_link_loss()
354 if ((link->cur_link_settings.lane_count != LANE_COUNT_UNKNOWN) || in dp_should_allow_hpd_rx_irq()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c62 for (lane = 0; lane < intel_dp->lane_count; lane++) { in intel_dp_get_adjust_train()
105 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
106 len = intel_dp->lane_count + 1; in intel_dp_set_link_train()
132 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
134 return ret == intel_dp->lane_count; in intel_dp_update_link_train()
141 for (lane = 0; lane < intel_dp->lane_count; lane++) in intel_dp_link_max_vswing_reached()
197 link_config[1] = intel_dp->lane_count; in intel_dp_link_training_clock_recovery()
245 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { in intel_dp_link_training_clock_recovery()
366 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
375 intel_dp->lane_count)) { in intel_dp_link_training_channel_equalization()
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H A Dintel_dp.h47 int link_rate, u8 lane_count,
50 int link_rate, u8 lane_count);
128 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
130 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
H A Dintel_dpio_phy.c579 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
581 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
589 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
669 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
682 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
690 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
698 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
721 for (i = 0; i < intel_crtc->config->lane_count; i++) { in chv_set_phy_signal_level()
735 if (intel_crtc->config->lane_count > 2) { in chv_set_phy_signal_level()
761 if (crtc_state->lane_count > in chv_data_lane_soft_reset()
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H A Dvlv_dsi.c43 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
47 8 * 100), lane_count); in txbyteclkhs()
51 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
54 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1083 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1135 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1137 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1139 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1189 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1281 unsigned int lane_count = intel_dsi->lane_count; set_dsi_timings() local
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H A Dvlv_dsi_pll.c44 int lane_count) in dsi_clk_from_pclk()
51 dsi_clk_khz = DIV_ROUND_CLOSEST(pclk * bpp, lane_count); in dsi_clk_from_pclk()
125 intel_dsi->lane_count); in vlv_dsi_pll_compute()
316 pclk = DIV_ROUND_CLOSEST(dsi_clock * intel_dsi->lane_count, bpp); in vlv_dsi_get_pclk()
337 pclk = DIV_ROUND_CLOSEST(dsi_clk * intel_dsi->lane_count, bpp); in bxt_dsi_get_pclk()
467 intel_dsi->lane_count); in bxt_dsi_pll_compute()
43 dsi_clk_from_pclk(u32 pclk, enum mipi_dsi_pixel_format fmt, int lane_count) dsi_clk_from_pclk() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/core/
H A Ddc_link_dp.c166 lt_settings->link_settings.lane_count; in dpcd_set_link_settings()
200 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
210 lt_settings->link_settings.lane_count, in dpcd_set_link_settings()
326 (uint32_t)(lt_settings->link_settings.lane_count); lane++) { in dpcd_set_lt_pattern_and_lane_settings()
343 size_in_bytes = lt_settings->link_settings.lane_count * sizeof(dpcd_lane[0]); in dpcd_set_lt_pattern_and_lane_settings()
431 for (lane = 0; lane < src.link_settings.lane_count; lane++) { in update_drive_settings()
493 for (lane = 1; lane < link_training_setting->link_settings.lane_count; in find_max_drive_settings()
551 max_lt_setting->link_settings.lane_count = in find_max_drive_settings()
552 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
557 link_training_setting->link_settings.lane_count; in find_max_drive_settings()
787 enum dc_lane_count lane_count = perform_post_lt_adj_req_sequence() local
923 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; perform_channel_equalization_sequence() local
1016 enum dc_lane_count lane_count = lt_settings->link_settings.lane_count; perform_clock_recovery_sequence() local
2177 reached_minimum_lane_count(enum dc_lane_count lane_count) reached_minimum_lane_count() argument
2187 reduce_lane_count(enum dc_lane_count lane_count) reduce_lane_count() argument
2217 increase_lane_count(enum dc_lane_count lane_count) increase_lane_count() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c261 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
263 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
268 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
273 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
277 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
289 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
315 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
320 lane_count); in analogix_dp_link_start()
335 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
348 analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane_count) analogix_dp_channel_eq_ok() argument
445 int lane, lane_count; analogix_dp_get_adjust_training_lane() local
468 int lane, lane_count, retval; analogix_dp_process_clock_recovery() local
540 int lane, lane_count, retval; analogix_dp_process_equalizer_training() local
627 analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, u8 *lane_count) analogix_dp_get_max_rx_lane_count() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/analogix/
H A Danalogix_dp_core.c262 int lane, lane_count, pll_tries, retval; in analogix_dp_link_start() local
264 lane_count = dp->link_train.lane_count; in analogix_dp_link_start()
269 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
274 analogix_dp_set_lane_count(dp, dp->link_train.lane_count); in analogix_dp_link_start()
278 buf[1] = dp->link_train.lane_count; in analogix_dp_link_start()
290 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
316 for (lane = 0; lane < lane_count; lane++) in analogix_dp_link_start()
321 lane_count); in analogix_dp_link_start()
336 static int analogix_dp_clock_recovery_ok(u8 link_status[2], int lane_count) in analogix_dp_clock_recovery_ok() argument
349 analogix_dp_channel_eq_ok(u8 link_status[2], u8 link_align, int lane_count) analogix_dp_channel_eq_ok() argument
446 int lane, lane_count; analogix_dp_get_adjust_training_lane() local
469 int lane, lane_count, retval; analogix_dp_process_clock_recovery() local
541 int lane, lane_count, retval; analogix_dp_process_equalizer_training() local
628 analogix_dp_get_max_rx_lane_count(struct analogix_dp_device *dp, u8 *lane_count) analogix_dp_get_max_rx_lane_count() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h87 * @lane_count: lane count requested by the sink
91 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
93 return (lane_count == 1 || in is_lane_count_valid()
94 lane_count == 2 || in is_lane_count_valid()
95 lane_count == 4); in is_lane_count_valid()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dp/
H A Ddp_panel.h92 * @lane_count: lane count requested by the sink
96 static inline bool is_lane_count_valid(u32 lane_count) in is_lane_count_valid() argument
98 return (lane_count == 1 || in is_lane_count_valid()
99 lane_count == 2 || in is_lane_count_valid()
100 lane_count == 4); in is_lane_count_valid()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dp_link_training.c330 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_tx_ffe_preset()
333 for (lane = 0; lane < crtc_state->lane_count; lane++) in intel_dp_get_lane_adjust_tx_ffe_preset()
353 lane = min(lane, crtc_state->lane_count - 1); in intel_dp_get_lane_adjust_vswing_preemph()
358 for (lane = 0; lane < crtc_state->lane_count; lane++) { in intel_dp_get_lane_adjust_vswing_preemph()
426 crtc_state->lane_count, in intel_dp_get_adjust_train()
433 crtc_state->lane_count, in intel_dp_get_adjust_train()
467 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); in intel_dp_set_link_train()
468 len = crtc_state->lane_count + 1; in intel_dp_set_link_train()
538 crtc_state->lane_count, in intel_dp_set_signal_levels()
545 crtc_state->lane_count, in intel_dp_set_signal_levels()
653 u8 lane_count = crtc_state->lane_count; intel_dp_update_link_bw_set() local
[all...]
H A Dintel_dp.h42 int link_rate, int lane_count);
44 int link_rate, u8 lane_count);
111 u32 link_clock, u32 lane_count,
122 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) in intel_dp_unused_lane_mask() argument
124 return ~((1 << lane_count) - 1) & 0xf; in intel_dp_unused_lane_mask()
H A Dintel_dpio_phy.c573 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) in bxt_ddi_phy_calc_lane_lat_optim_mask() argument
575 switch (lane_count) { in bxt_ddi_phy_calc_lane_lat_optim_mask()
583 MISSING_CASE(lane_count); in bxt_ddi_phy_calc_lane_lat_optim_mask()
705 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
718 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
726 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
734 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
757 for (i = 0; i < crtc_state->lane_count; i++) { in chv_set_phy_signal_level()
771 if (crtc_state->lane_count > 2) { in chv_set_phy_signal_level()
797 if (crtc_state->lane_count > in chv_data_lane_soft_reset()
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H A Dvlv_dsi.c52 static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, in txbyteclkhs() argument
56 8 * 100), lane_count); in txbyteclkhs()
60 static u16 pixels_from_txbyteclkhs(u16 clk_hs, int bpp, int lane_count, in pixels_from_txbyteclkhs() argument
63 return DIV_ROUND_UP((clk_hs * lane_count * 8 * 100), in pixels_from_txbyteclkhs()
1016 unsigned int lane_count = intel_dsi->lane_count; in bxt_dsi_get_pipe_config() local
1068 hfp = pixels_from_txbyteclkhs(hfp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1070 hsync = pixels_from_txbyteclkhs(hsync, bpp, lane_count, in bxt_dsi_get_pipe_config()
1072 hbp = pixels_from_txbyteclkhs(hbp, bpp, lane_count, in bxt_dsi_get_pipe_config()
1121 hfp_sw = txbyteclkhs(hfp_sw, bpp, lane_count, in bxt_dsi_get_pipe_config()
1217 unsigned int lane_count = intel_dsi->lane_count; set_dsi_timings() local
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H A Dintel_combo_phy.c263 int lane_count, bool lane_reversal) in intel_combo_phy_power_up_lanes()
270 switch (lane_count) { in intel_combo_phy_power_up_lanes()
281 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
288 switch (lane_count) { in intel_combo_phy_power_up_lanes()
298 MISSING_CASE(lane_count); in intel_combo_phy_power_up_lanes()
261 intel_combo_phy_power_up_lanes(struct drm_i915_private *dev_priv, enum phy phy, bool is_dsi, int lane_count, bool lane_reversal) intel_combo_phy_power_up_lanes() argument
/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c266 uint8_t lane_count; member
902 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
915 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
917 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
921 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
925 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
933 intel_dp->lane_count in cdv_intel_dp_mode_fixup()
995 int lane_count = 4, bpp = 24; cdv_intel_dp_set_m_n() local
1319 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) cdv_intel_clock_recovery_ok() argument
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/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A Dcdv_intel_dp.c262 uint8_t lane_count; member
898 int lane_count, clock; in cdv_intel_dp_mode_fixup() local
911 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { in cdv_intel_dp_mode_fixup()
913 int link_avail = cdv_intel_dp_max_data_rate(cdv_intel_dp_link_clock(bws[clock]), lane_count); in cdv_intel_dp_mode_fixup()
917 intel_dp->lane_count = lane_count; in cdv_intel_dp_mode_fixup()
921 intel_dp->link_bw, intel_dp->lane_count, in cdv_intel_dp_mode_fixup()
929 intel_dp->lane_count in cdv_intel_dp_mode_fixup()
991 int lane_count = 4, bpp = 24; cdv_intel_dp_set_m_n() local
1315 cdv_intel_clock_recovery_ok(uint8_t link_status[DP_LINK_STATUS_SIZE], int lane_count) cdv_intel_clock_recovery_ok() argument
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/kernel/linux/linux-5.10/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c55 u32 lane_count; member
185 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
500 &ps8622->lane_count)) { in ps8622_probe()
501 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
502 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
505 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
/kernel/linux/linux-6.6/drivers/gpu/drm/bridge/
H A Dparade-ps8622.c54 u32 lane_count; member
184 err = ps8622_set(cl, 0x01, 0x21, 0x80 | ps8622->lane_count); in ps8622_send_config()
490 &ps8622->lane_count)) { in ps8622_probe()
491 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()
492 } else if (ps8622->lane_count > ps8622->max_lane_count) { in ps8622_probe()
495 ps8622->lane_count = ps8622->max_lane_count; in ps8622_probe()

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