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Help
Searched
refs:io_p2v
(Results
1 - 25
of
36
) sorted by relevance
1
2
/kernel/linux/linux-5.10/arch/arm/mach-pxa/include/mach/
H
A
D
regs-ost.h
11
#define OSMR0
io_p2v
(0x40A00000) /* */
12
#define OSMR1
io_p2v
(0x40A00004) /* */
13
#define OSMR2
io_p2v
(0x40A00008) /* */
14
#define OSMR3
io_p2v
(0x40A0000C) /* */
15
#define OSMR4
io_p2v
(0x40A00080) /* */
16
#define OSCR
io_p2v
(0x40A00010) /* OS Timer Counter Register */
17
#define OSCR4
io_p2v
(0x40A00040) /* OS Timer Counter Register */
18
#define OMCR4
io_p2v
(0x40A000C0) /* */
19
#define OSSR
io_p2v
(0x40A00014) /* OS Timer Status Register */
20
#define OWER
io_p2v
(
[all...]
H
A
D
mtd-xip.h
19
#define ICIP
io_p2v
(0x40d00000)
20
#define ICMR
io_p2v
(0x40d00004)
H
A
D
pxa2xx-regs.h
134
#define CCCR
io_p2v
(0x41300000) /* Core Clock Configuration Register */
135
#define CCSR
io_p2v
(0x4130000C) /* Core Clock Status Register */
136
#define CKEN
io_p2v
(0x41300004) /* Clock Enable Register */
137
#define OSCC
io_p2v
(0x41300008) /* Oscillator Configuration Register */
H
A
D
hardware.h
37
#define
io_p2v
(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
macro
40
# define __REG(x) (*((volatile u32 __iomem *)
io_p2v
(x)))
42
/* With indexed regs we don't want to feed the index through
io_p2v
()
51
# define __REG(x)
io_p2v
(x)
H
A
D
dma.h
15
#define DMAC_REGS_VIRT
io_p2v
(0x40000000)
H
A
D
pxa3xx-regs.h
18
#define OSCC
io_p2v
(0x41350000) /* Oscillator Configuration Register */
/kernel/linux/linux-6.6/arch/arm/mach-pxa/
H
A
D
regs-ost.h
13
#define OSMR0
io_p2v
(0x40A00000) /* */
14
#define OSMR1
io_p2v
(0x40A00004) /* */
15
#define OSMR2
io_p2v
(0x40A00008) /* */
16
#define OSMR3
io_p2v
(0x40A0000C) /* */
17
#define OSMR4
io_p2v
(0x40A00080) /* */
18
#define OSCR
io_p2v
(0x40A00010) /* OS Timer Counter Register */
19
#define OSCR4
io_p2v
(0x40A00040) /* OS Timer Counter Register */
20
#define OMCR4
io_p2v
(0x40A000C0) /* */
21
#define OSSR
io_p2v
(0x40A00014) /* OS Timer Status Register */
22
#define OWER
io_p2v
(
[all...]
H
A
D
generic.c
52
pxa25x_clocks_init(
io_p2v
(0x41300000));
in pxa_timer_init()
54
pxa27x_clocks_init(
io_p2v
(0x41300000));
in pxa_timer_init()
56
pxa3xx_clocks_init(
io_p2v
(0x41340000),
io_p2v
(0x41350000));
in pxa_timer_init()
57
pxa_timer_nodt_init(IRQ_OST0,
io_p2v
(0x40a00000));
in pxa_timer_init()
H
A
D
pxa-regs.h
32
#define
io_p2v
(x) IOMEM(0xf2000000 + ((x) & 0x01ffffff) + (((x) & 0x1c000000) >> 1))
macro
35
# define __REG(x) (*((volatile u32 __iomem *)
io_p2v
(x)))
37
/* With indexed regs we don't want to feed the index through
io_p2v
()
46
# define __REG(x)
io_p2v
(x)
H
A
D
pxa2xx-regs.h
134
#define CCCR
io_p2v
(0x41300000) /* Core Clock Configuration Register */
135
#define CCSR
io_p2v
(0x4130000C) /* Core Clock Status Register */
136
#define CKEN
io_p2v
(0x41300004) /* Clock Enable Register */
137
#define OSCC
io_p2v
(0x41300008) /* Oscillator Configuration Register */
H
A
D
irq.c
173
pxa_irq_base =
io_p2v
(0x40d00000);
in pxa_init_irq()
258
pxa_irq_base =
io_p2v
(res.start);
in pxa_dt_irq_init()
H
A
D
pxa3xx-regs.h
18
#define OSCC
io_p2v
(0x41350000) /* Oscillator Configuration Register */
/kernel/linux/linux-5.10/arch/arm/mach-lpc32xx/
H
A
D
lpc32xx.h
121
#define _PMREG(x)
io_p2v
(LPC32XX_CLK_PM_BASE +\
576
#define LPC32XX_INTC_MASK(x)
io_p2v
((x) + 0x00)
577
#define LPC32XX_INTC_RAW_STAT(x)
io_p2v
((x) + 0x04)
578
#define LPC32XX_INTC_STAT(x)
io_p2v
((x) + 0x08)
579
#define LPC32XX_INTC_POLAR(x)
io_p2v
((x) + 0x0C)
580
#define LPC32XX_INTC_ACT_TYPE(x)
io_p2v
((x) + 0x10)
581
#define LPC32XX_INTC_TYPE(x)
io_p2v
((x) + 0x14)
586
#define LPC32XX_TIMER_IR(x)
io_p2v
((x) + 0x00)
587
#define LPC32XX_TIMER_TCR(x)
io_p2v
((x) + 0x04)
588
#define LPC32XX_TIMER_TC(x)
io_p2v
((
714
#define
io_p2v
global()
macro
[all...]
H
A
D
common.c
41
iramptr1 =
io_p2v
(LPC32XX_IRAM_BASE);
in lpc32xx_return_iram()
42
iramptr2 =
io_p2v
(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
in lpc32xx_return_iram()
59
*mapbase =
io_p2v
(LPC32XX_IRAM_BASE);
in lpc32xx_return_iram()
H
A
D
pm.c
124
#define EMC_CTRL_REG
io_p2v
(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
/kernel/linux/linux-6.6/arch/arm/mach-lpc32xx/
H
A
D
lpc32xx.h
121
#define _PMREG(x)
io_p2v
(LPC32XX_CLK_PM_BASE +\
576
#define LPC32XX_INTC_MASK(x)
io_p2v
((x) + 0x00)
577
#define LPC32XX_INTC_RAW_STAT(x)
io_p2v
((x) + 0x04)
578
#define LPC32XX_INTC_STAT(x)
io_p2v
((x) + 0x08)
579
#define LPC32XX_INTC_POLAR(x)
io_p2v
((x) + 0x0C)
580
#define LPC32XX_INTC_ACT_TYPE(x)
io_p2v
((x) + 0x10)
581
#define LPC32XX_INTC_TYPE(x)
io_p2v
((x) + 0x14)
586
#define LPC32XX_TIMER_IR(x)
io_p2v
((x) + 0x00)
587
#define LPC32XX_TIMER_TCR(x)
io_p2v
((x) + 0x04)
588
#define LPC32XX_TIMER_TC(x)
io_p2v
((
714
#define
io_p2v
global()
macro
[all...]
H
A
D
common.c
41
iramptr1 =
io_p2v
(LPC32XX_IRAM_BASE);
in lpc32xx_return_iram()
42
iramptr2 =
io_p2v
(LPC32XX_IRAM_BASE + LPC32XX_IRAM_BANK_SIZE);
in lpc32xx_return_iram()
59
*mapbase =
io_p2v
(LPC32XX_IRAM_BASE);
in lpc32xx_return_iram()
H
A
D
pm.c
122
#define EMC_CTRL_REG
io_p2v
(LPC32XX_EMC_BASE + EMC_DYN_MEM_CTRL_OFS)
/kernel/linux/linux-5.10/arch/arm/mach-sa1100/include/mach/
H
A
D
hardware.h
35
#define
io_p2v
( x ) \
macro
40
#define __MREG(x) IOMEM(
io_p2v
(x))
44
# define __REG(x) (*((volatile unsigned long __iomem *)
io_p2v
(x)))
49
# define __REG(x)
io_p2v
(x)
H
A
D
SA-1100.h
834
#define OSMR0
io_p2v
(0x90000000) /* OS timer Match Reg. 0 */
835
#define OSMR1
io_p2v
(0x90000004) /* OS timer Match Reg. 1 */
836
#define OSMR2
io_p2v
(0x90000008) /* OS timer Match Reg. 2 */
837
#define OSMR3
io_p2v
(0x9000000c) /* OS timer Match Reg. 3 */
838
#define OSCR
io_p2v
(0x90000010) /* OS timer Counter Reg. */
839
#define OSSR
io_p2v
(0x90000014) /* OS timer Status Reg. */
840
#define OWER
io_p2v
(0x90000018) /* OS timer Watch-dog Enable Reg. */
841
#define OIER
io_p2v
(0x9000001C) /* OS timer Interrupt Enable Reg. */
/kernel/linux/linux-6.6/arch/arm/mach-sa1100/include/mach/
H
A
D
hardware.h
35
#define
io_p2v
( x ) \
macro
40
#define __MREG(x) IOMEM(
io_p2v
(x))
44
# define __REG(x) (*((volatile unsigned long __iomem *)
io_p2v
(x)))
49
# define __REG(x)
io_p2v
(x)
H
A
D
SA-1100.h
834
#define OSMR0
io_p2v
(0x90000000) /* OS timer Match Reg. 0 */
835
#define OSMR1
io_p2v
(0x90000004) /* OS timer Match Reg. 1 */
836
#define OSMR2
io_p2v
(0x90000008) /* OS timer Match Reg. 2 */
837
#define OSMR3
io_p2v
(0x9000000c) /* OS timer Match Reg. 3 */
838
#define OSCR
io_p2v
(0x90000010) /* OS timer Counter Reg. */
839
#define OSSR
io_p2v
(0x90000014) /* OS timer Status Reg. */
840
#define OWER
io_p2v
(0x90000018) /* OS timer Watch-dog Enable Reg. */
841
#define OIER
io_p2v
(0x9000001C) /* OS timer Interrupt Enable Reg. */
/kernel/linux/linux-5.10/arch/arm/mach-pxa/
H
A
D
irq.c
172
pxa_irq_base =
io_p2v
(0x40d00000);
in pxa_init_irq()
257
pxa_irq_base =
io_p2v
(res.start);
in pxa_dt_irq_init()
H
A
D
generic.c
54
pxa_timer_nodt_init(IRQ_OST0,
io_p2v
(0x40a00000));
in pxa_timer_init()
H
A
D
pxa320.c
80
mfp_init_base(
io_p2v
(MFPR_BASE));
in pxa320_init()
Completed in 22 milliseconds
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