| /kernel/linux/linux-5.10/drivers/pinctrl/qcom/ |
| H A D | pinctrl-msm.h | 34 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
45 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
51 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
52 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
53 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
68 u32 intr_cfg_reg; member
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| H A D | pinctrl-qdf2xxx.c | 107 groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; in qdf2xxx_pinctrl_probe()
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| H A D | pinctrl-ipq8064.c | 192 .intr_cfg_reg = 0x1008 + 0x10 * id, \
219 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sc7180.c | 50 .intr_cfg_reg = 0x1000 * id + 0x8, \
77 .intr_cfg_reg = 0, \
103 .intr_cfg_reg = 0, \
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| H A D | pinctrl-msm8x74.c | 353 .intr_cfg_reg = 0x1008 + 0x10 * id, \
379 .intr_cfg_reg = 0, \
410 .intr_cfg_reg = 0, \
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| H A D | pinctrl-msm8226.c | 291 .intr_cfg_reg = 0x1008 + 0x10 * id, \
317 .intr_cfg_reg = 0, \
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| H A D | pinctrl-apq8064.c | 240 .intr_cfg_reg = 0x1008 + 0x10 * id, \
267 .intr_cfg_reg = 0, \
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| H A D | pinctrl-qcs404.c | 52 .intr_cfg_reg = 0x1000 * id + 0x8, \
79 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sdm660.c | 56 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
83 .intr_cfg_reg = 0, \
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| H A D | pinctrl-msm8916.c | 316 .intr_cfg_reg = 0x8 + 0x1000 * id, \
342 .intr_cfg_reg = 0, \
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| /kernel/linux/linux-6.6/drivers/pinctrl/qcom/ |
| H A D | pinctrl-msm.h | 47 * @intr_cfg_reg: Offset of the register holding interrupt configuration bits.
58 * @intr_enable_bit: Offset in @intr_cfg_reg for enabling the interrupt for this group.
65 * @intr_raw_status_bit: Offset in @intr_cfg_reg for the raw status bit.
66 * @intr_polarity_bit: Offset in @intr_cfg_reg for specifying polarity of the interrupt.
67 * @intr_detection_bit: Offset in @intr_cfg_reg for specifying interrupt type.
80 u32 intr_cfg_reg; member
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| H A D | pinctrl-qdf2xxx.c | 107 groups[gpio].intr_cfg_reg = 0x08 + 0x10000 * gpio; in qdf2xxx_pinctrl_probe()
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| H A D | pinctrl-sdm670.c | 38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
68 .intr_cfg_reg = 0, \
93 .intr_cfg_reg = 0, \
118 .intr_cfg_reg = 0, \
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| H A D | pinctrl-ipq8064.c | 184 .intr_cfg_reg = 0x1008 + 0x10 * id, \
211 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sm6125.c | 41 .intr_cfg_reg = 0x8 + 0x1000 * id, \
68 .intr_cfg_reg = 0, \
94 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sdx65.c | 34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
60 .intr_cfg_reg = 0, \
85 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sm6115.c | 44 .intr_cfg_reg = 0x8 + 0x1000 * id, \
71 .intr_cfg_reg = 0, \
97 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sc7180.c | 42 .intr_cfg_reg = 0x1000 * id + 0x8, \
69 .intr_cfg_reg = 0, \
95 .intr_cfg_reg = 0, \
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| H A D | pinctrl-qdu1000.c | 36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
62 .intr_cfg_reg = 0, \
87 .intr_cfg_reg = 0, \
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| H A D | pinctrl-msm8x74.c | 345 .intr_cfg_reg = 0x1008 + 0x10 * id, \
371 .intr_cfg_reg = 0, \
402 .intr_cfg_reg = 0, \
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| H A D | pinctrl-qcm2290.c | 34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
60 .intr_cfg_reg = 0, \
85 .intr_cfg_reg = 0, \
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| H A D | pinctrl-sm7150.c | 48 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
75 .intr_cfg_reg = 0, \
101 .intr_cfg_reg = 0, \
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| H A D | pinctrl-msm8226.c | 283 .intr_cfg_reg = 0x1008 + 0x10 * id, \
309 .intr_cfg_reg = 0, \
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| H A D | pinctrl-apq8064.c | 232 .intr_cfg_reg = 0x1008 + 0x10 * id, \
259 .intr_cfg_reg = 0, \
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| H A D | pinctrl-mdm9607.c | 226 .intr_cfg_reg = 0x8 + 0x1000 * id, \
252 .intr_cfg_reg = 0, \
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