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Searched refs:inst_mask (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dmmhub_v1_8.c58 u32 inst_mask; in mmhub_v1_8_setup_vm_pt_regs() local
61 inst_mask = adev->aid_mask; in mmhub_v1_8_setup_vm_pt_regs()
62 for_each_inst(i, inst_mask) { in mmhub_v1_8_setup_vm_pt_regs()
79 u32 inst_mask; in mmhub_v1_8_init_gart_aperture_regs() local
92 inst_mask = adev->aid_mask; in mmhub_v1_8_init_gart_aperture_regs()
93 for_each_inst(i, inst_mask) { in mmhub_v1_8_init_gart_aperture_regs()
129 uint32_t tmp, inst_mask; in mmhub_v1_8_init_system_aperture_regs() local
136 inst_mask = adev->aid_mask; in mmhub_v1_8_init_system_aperture_regs()
137 for_each_inst(i, inst_mask) { in mmhub_v1_8_init_system_aperture_regs()
192 uint32_t tmp, inst_mask; in mmhub_v1_8_init_tlb_regs() local
218 uint32_t tmp, inst_mask; mmhub_v1_8_init_cache_regs() local
279 uint32_t tmp, inst_mask; mmhub_v1_8_enable_system_domain() local
299 u32 inst_mask; mmhub_v1_8_disable_identity_aperture() local
332 uint32_t tmp, inst_mask; mmhub_v1_8_setup_vmid_config() local
398 u32 i, j, inst_mask; mmhub_v1_8_program_invalidation() local
434 u32 i, j, inst_mask; mmhub_v1_8_gart_disable() local
471 u32 tmp, inst_mask; mmhub_v1_8_set_fault_enable_default() local
517 u32 inst_mask; mmhub_v1_8_init() local
651 uint32_t inst_mask; mmhub_v1_8_query_ras_error_count() local
679 uint32_t inst_mask; mmhub_v1_8_reset_ras_error_count() local
735 uint32_t inst_mask; mmhub_v1_8_query_ras_error_status() local
820 uint32_t inst_mask; mmhub_v1_8_reset_ras_error_status() local
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H A Dsdma_v4_4_2.c100 uint32_t inst_mask) in sdma_v4_4_2_inst_init_golden_registers()
421 * @inst_mask: mask of dma engine instances to be disabled
426 uint32_t inst_mask) in sdma_v4_4_2_inst_gfx_stop()
432 for_each_inst(i, inst_mask) { in sdma_v4_4_2_inst_gfx_stop()
453 * @inst_mask: mask of dma engine instances to be disabled
458 uint32_t inst_mask) in sdma_v4_4_2_inst_rlc_stop()
467 * @inst_mask: mask of dma engine instances to be disabled
472 uint32_t inst_mask) in sdma_v4_4_2_inst_page_stop()
479 for_each_inst(i, inst_mask) { in sdma_v4_4_2_inst_page_stop()
504 * @inst_mask
99 sdma_v4_4_2_inst_init_golden_registers(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_init_golden_registers() argument
425 sdma_v4_4_2_inst_gfx_stop(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_gfx_stop() argument
457 sdma_v4_4_2_inst_rlc_stop(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_rlc_stop() argument
471 sdma_v4_4_2_inst_page_stop(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_page_stop() argument
508 sdma_v4_4_2_inst_ctx_switch_enable(struct amdgpu_device *adev, bool enable, uint32_t inst_mask) sdma_v4_4_2_inst_ctx_switch_enable() argument
563 sdma_v4_4_2_inst_enable(struct amdgpu_device *adev, bool enable, uint32_t inst_mask) sdma_v4_4_2_inst_enable() argument
800 sdma_v4_4_2_inst_rlc_resume(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_rlc_resume() argument
817 sdma_v4_4_2_inst_load_microcode(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_load_microcode() argument
862 sdma_v4_4_2_inst_start(struct amdgpu_device *adev, uint32_t inst_mask) sdma_v4_4_2_inst_start() argument
1416 uint32_t inst_mask; sdma_v4_4_2_hw_init() local
1430 uint32_t inst_mask; sdma_v4_4_2_hw_fini() local
1699 sdma_v4_4_2_inst_update_medium_grain_light_sleep( struct amdgpu_device *adev, bool enable, uint32_t inst_mask) sdma_v4_4_2_inst_update_medium_grain_light_sleep() argument
1728 sdma_v4_4_2_inst_update_medium_grain_clock_gating( struct amdgpu_device *adev, bool enable, uint32_t inst_mask) sdma_v4_4_2_inst_update_medium_grain_clock_gating() argument
1769 uint32_t inst_mask; sdma_v4_4_2_set_clockgating_state() local
2059 sdma_v4_4_2_xcp_resume(void *handle, uint32_t inst_mask) sdma_v4_4_2_xcp_resume() argument
2072 sdma_v4_4_2_xcp_suspend(void *handle, uint32_t inst_mask) sdma_v4_4_2_xcp_suspend() argument
2149 uint32_t inst_mask; sdma_v4_4_2_query_ras_error_count() local
2174 uint32_t inst_mask; sdma_v4_4_2_reset_ras_error_count() local
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H A Daqua_vanjaram.c69 uint32_t inst_mask; in aqua_vanjaram_set_xcp_id() local
75 inst_mask = 1 << inst_idx; in aqua_vanjaram_set_xcp_id()
90 inst_mask = 1 << (inst_idx * 2); in aqua_vanjaram_set_xcp_id()
98 if (adev->xcp_mgr->xcp[xcp_id].ip[ip_blk].inst_mask & inst_mask) { in aqua_vanjaram_set_xcp_id()
251 uint32_t inst_mask) in aqua_vanjaram_populate_ip_map()
255 while (inst_mask) { in aqua_vanjaram_populate_ip_map()
256 i = ffs(inst_mask) - 1; in aqua_vanjaram_populate_ip_map()
258 inst_mask &= ~(1 << i); in aqua_vanjaram_populate_ip_map()
269 { VCN_HWIP, adev->vcn.inst_mask }, in aqua_vanjaram_ip_map_init()
249 aqua_vanjaram_populate_ip_map(struct amdgpu_device *adev, enum amd_hw_ip_block_type ip_block, uint32_t inst_mask) aqua_vanjaram_populate_ip_map() argument
625 u32 mask, inst_mask = adev->sdma.sdma_mask; aqua_vanjaram_init_soc_config() local
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H A Damdgpu_xcp.h60 int (*prepare_suspend)(void *handle, uint32_t inst_mask);
61 int (*suspend)(void *handle, uint32_t inst_mask);
62 int (*prepare_resume)(void *handle, uint32_t inst_mask);
63 int (*resume)(void *handle, uint32_t inst_mask);
68 uint32_t inst_mask; member
137 uint32_t *inst_mask);
H A Damdgpu_xcp.c33 int (*run_func)(void *handle, uint32_t inst_mask); in __amdgpu_xcp_run()
57 ret = run_func(xcp_mgr->adev, xcp_ip->inst_mask); in __amdgpu_xcp_run()
305 (xcp->ip[ip].inst_mask & BIT(instance))) in amdgpu_xcp_get_partition()
317 uint32_t *inst_mask) in amdgpu_xcp_get_inst_details()
319 if (!xcp->valid || !inst_mask || !(xcp->ip[ip].valid)) in amdgpu_xcp_get_inst_details()
322 *inst_mask = xcp->ip[ip].inst_mask; in amdgpu_xcp_get_inst_details()
315 amdgpu_xcp_get_inst_details(struct amdgpu_xcp *xcp, enum AMDGPU_XCP_IP_BLOCK ip, uint32_t *inst_mask) amdgpu_xcp_get_inst_details() argument
H A Damdgpu_jpeg.h64 uint16_t inst_mask; member
H A Dgfxhub_v1_2.c627 static int gfxhub_v1_2_xcp_resume(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_resume() argument
637 gfxhub_v1_2_xcc_set_fault_enable_default(adev, value, inst_mask); in gfxhub_v1_2_xcp_resume()
640 return gfxhub_v1_2_xcc_gart_enable(adev, inst_mask); in gfxhub_v1_2_xcp_resume()
645 static int gfxhub_v1_2_xcp_suspend(void *handle, uint32_t inst_mask) in gfxhub_v1_2_xcp_suspend() argument
650 gfxhub_v1_2_xcc_gart_disable(adev, inst_mask); in gfxhub_v1_2_xcp_suspend()
H A Dnbio_v7_9.c426 u32 inst_mask; in nbio_v7_9_init_registers() local
440 inst_mask = adev->aid_mask & ~1U; in nbio_v7_9_init_registers()
441 for_each_inst(i, inst_mask) { in nbio_v7_9_init_registers()
H A Damdgpu_discovery.c337 adev->vcn.inst_mask &= ~AMDGPU_VCN_HARVEST_VCN1; in amdgpu_discovery_harvest_config_quirk()
576 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
578 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
582 adev->vcn.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
584 adev->jpeg.inst_mask &= in amdgpu_discovery_read_harvest_bit_per_ip()
636 adev->vcn.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
638 adev->jpeg.inst_mask &= in amdgpu_discovery_read_from_harvest_table()
924 harvest = ((1 << inst) & adev->vcn.inst_mask) == 0; in amdgpu_discovery_get_harvest_info()
1227 adev->vcn.inst_mask = 0; in amdgpu_discovery_reg_base_init()
1228 adev->jpeg.inst_mask in amdgpu_discovery_reg_base_init()
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H A Damdgpu_vcn.h285 uint16_t inst_mask; member
H A Damdgpu_ras.c340 uint32_t mask, inst_mask = data->inject.instance_mask; in amdgpu_ras_instance_mask_check() local
343 if (num_xcc <= 1 && inst_mask) { in amdgpu_ras_instance_mask_check()
347 inst_mask); in amdgpu_ras_instance_mask_check()
364 mask = inst_mask; in amdgpu_ras_instance_mask_check()
370 if (inst_mask != data->inject.instance_mask) in amdgpu_ras_instance_mask_check()
373 inst_mask, data->inject.instance_mask); in amdgpu_ras_instance_mask_check()
H A Damdgpu.h1283 #define for_each_inst(i, inst_mask) \
1284 for (i = ffs(inst_mask); i-- != 0; \
1285 i = ffs(inst_mask & BIT_MASK_UPPER(i + 1)))
H A Dgmc_v9_0.c2018 unsigned long inst_mask = adev->aid_mask; in gmc_v9_0_sw_init() local
2115 inst_mask <<= AMDGPU_MMHUB0(0); in gmc_v9_0_sw_init()
2116 bitmap_or(adev->vmhubs_mask, adev->vmhubs_mask, &inst_mask, 32); in gmc_v9_0_sw_init()
H A Dgfx_v9_4_3.c4361 static int gfx_v9_4_3_xcp_resume(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_resume() argument
4370 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4375 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4383 tmp_mask = inst_mask; in gfx_v9_4_3_xcp_resume()
4393 static int gfx_v9_4_3_xcp_suspend(void *handle, uint32_t inst_mask) in gfx_v9_4_3_xcp_suspend() argument
4398 for_each_inst(i, inst_mask) in gfx_v9_4_3_xcp_suspend()

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