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Searched refs:i915_mmio_reg_offset (Results 1 - 25 of 87) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c154 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
332 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
334 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
361 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
367 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
369 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
415 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
473 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
484 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
490 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IR in gen8_check_pending_irq()
[all...]
H A Dedid.c381 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
383 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
411 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
413 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
415 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
417 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
H A Dscheduler.c88 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
89 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
90 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
91 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
92 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
110 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
256 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
260 vgpu_vreg(vgpu, i915_mmio_reg_offset(re in save_ring_hw_state()
[all...]
H A Dmmio_context.c222 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
252 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
279 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
535 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c157 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
335 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
337 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
364 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
370 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
372 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
454 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
512 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
523 reg_base = i915_mmio_reg_offset(info->reg_base); in gen8_check_pending_irq()
529 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IR in gen8_check_pending_irq()
[all...]
H A Dedid.c384 if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_read()
386 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_read()
414 if (offset == i915_mmio_reg_offset(PCH_GMBUS0)) in intel_gvt_i2c_handle_gmbus_write()
416 else if (offset == i915_mmio_reg_offset(PCH_GMBUS1)) in intel_gvt_i2c_handle_gmbus_write()
418 else if (offset == i915_mmio_reg_offset(PCH_GMBUS2)) in intel_gvt_i2c_handle_gmbus_write()
420 else if (offset == i915_mmio_reg_offset(PCH_GMBUS3)) in intel_gvt_i2c_handle_gmbus_write()
H A Dscheduler.c92 i915_mmio_reg_offset(EU_PERF_CNTL0), in sr_oa_regs()
93 i915_mmio_reg_offset(EU_PERF_CNTL1), in sr_oa_regs()
94 i915_mmio_reg_offset(EU_PERF_CNTL2), in sr_oa_regs()
95 i915_mmio_reg_offset(EU_PERF_CNTL3), in sr_oa_regs()
96 i915_mmio_reg_offset(EU_PERF_CNTL4), in sr_oa_regs()
97 i915_mmio_reg_offset(EU_PERF_CNTL5), in sr_oa_regs()
98 i915_mmio_reg_offset(EU_PERF_CNTL6), in sr_oa_regs()
114 i915_mmio_reg_offset(GEN8_OACTXCONTROL); in sr_oa_regs()
274 vgpu_vreg(vgpu, i915_mmio_reg_offset(reg)) = in save_ring_hw_state()
278 vgpu_vreg(vgpu, i915_mmio_reg_offset(re in save_ring_hw_state()
[all...]
H A Dmmio_context.c228 *cs++ = i915_mmio_reg_offset(mmio->reg); in restore_context_mmio_for_inhibit()
258 *cs++ = i915_mmio_reg_offset(GEN9_GFX_MOCS(index)); in restore_render_mocs_control_for_inhibit()
285 *cs++ = i915_mmio_reg_offset(GEN9_LNCFCMOCS(index)); in restore_render_mocs_l3cc_for_inhibit()
541 i915_mmio_reg_offset(mmio->reg), in switch_mmio()
H A Dhandlers.c167 ((offset - i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0))) >> 3)
170 (num * 8 + i915_mmio_reg_offset(FENCE_REG_GEN6_LO(0)))
784 reg_nonpriv != i915_mmio_reg_offset(RING_NOPID(engine->mmio_base))) { in force_nonpriv_write()
802 if (offset == i915_mmio_reg_offset(DDI_BUF_CTL(PORT_E))) in ddi_buf_ctl_mmio_write()
884 end = i915_mmio_reg_offset(i915_end); in calc_index()
1079 if (reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_A))) in trigger_aux_channel_interrupt()
1082 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_B))) in trigger_aux_channel_interrupt()
1085 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_C))) in trigger_aux_channel_interrupt()
1088 reg == i915_mmio_reg_offset(DP_AUX_CH_CTL(AUX_CH_D))) in trigger_aux_channel_interrupt()
1959 offset == i915_mmio_reg_offset(RING_TIMESTAM in mmio_read_from_hw()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gt/
H A Dintel_lrc.c1261 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1269 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1270 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1275 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_timestamp_wa()
1276 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0)); in gen12_emit_timestamp_wa()
1289 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_restore_scratch()
1305 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1313 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0)); in gen12_emit_cmd_buf_wa()
1314 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0)); in gen12_emit_cmd_buf_wa()
1328 *cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBU in dg2_emit_rcs_hang_wabb()
[all...]
H A Dselftest_lrc.c304 i915_mmio_reg_offset(RING_START(engine->mmio_base)), in live_lrc_fixed()
309 i915_mmio_reg_offset(RING_CTL(engine->mmio_base)), in live_lrc_fixed()
314 i915_mmio_reg_offset(RING_HEAD(engine->mmio_base)), in live_lrc_fixed()
319 i915_mmio_reg_offset(RING_TAIL(engine->mmio_base)), in live_lrc_fixed()
324 i915_mmio_reg_offset(RING_MI_MODE(engine->mmio_base)), in live_lrc_fixed()
329 i915_mmio_reg_offset(RING_BBSTATE(engine->mmio_base)), in live_lrc_fixed()
334 i915_mmio_reg_offset(RING_BB_PER_CTX_PTR(engine->mmio_base)), in live_lrc_fixed()
339 i915_mmio_reg_offset(RING_INDIRECT_CTX(engine->mmio_base)), in live_lrc_fixed()
344 i915_mmio_reg_offset(RING_INDIRECT_CTX_OFFSET(engine->mmio_base)), in live_lrc_fixed()
349 i915_mmio_reg_offset(RING_CTX_TIMESTAM in live_lrc_fixed()
[all...]
H A Dselftest_workarounds.c157 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
184 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
465 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
520 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
870 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
906 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
961 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
965 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
989 i915_mmio_reg_offset(reg), a, b); in result_eq()
1011 i915_mmio_reg_offset(re in result_neq()
[all...]
H A Dintel_ring_submission.c666 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
670 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
675 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
680 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
728 *cs++ = i915_mmio_reg_offset( in mi_set_context()
783 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
790 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
825 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
H A Dintel_workarounds.c144 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
173 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
175 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
183 i915_mmio_reg_offset(wa_->reg), in _wa_add()
202 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
203 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
204 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
205 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
1023 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1889 name, from, i915_mmio_reg_offset(w in wa_verify()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_reg_defs.h282 #define i915_mmio_reg_offset(r) \ macro
284 #define i915_mmio_reg_equal(a, b) (i915_mmio_reg_offset(a) == i915_mmio_reg_offset(b))
H A Dintel_uncore.h329 u32 offset = i915_mmio_reg_offset(reg); \
339 u32 offset = i915_mmio_reg_offset(reg); \
517 readl(base + i915_mmio_reg_offset(reg))
519 writel(value, base + i915_mmio_reg_offset(reg))
H A Di915_perf.c1358 *cs++ = i915_mmio_reg_offset(reg); in __store_reg_to_mem()
1521 offset = oa_context_image_offset(ce, i915_mmio_reg_offset(reg)); in set_oa_ctx_ctrl_offset()
1957 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
2054 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4; in alloc_noa_wait()
2057 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
2058 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
2072 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
2075 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
2076 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
2095 *cs++ = i915_mmio_reg_offset(CS_GP in alloc_noa_wait()
[all...]
H A Di915_ioctl.c55 u32 entry_offset = i915_mmio_reg_offset(entry->offset_ldw); in i915_reg_read_ioctl()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gt/
H A Dselftest_workarounds.c159 *cs++ = i915_mmio_reg_offset(RING_FORCE_TO_NONPRIV(base, i)); in read_nonprivs()
186 return i915_mmio_reg_offset(reg); in get_whitelist_reg()
449 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in whitelist_writable_count()
503 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in check_dirty_whitelist()
821 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in read_whitelisted_registers()
860 u32 reg = i915_mmio_reg_offset(engine->whitelist.list[i].reg); in scrub_whitelisted_registers()
919 u32 offset = i915_mmio_reg_offset(reg); in find_reg()
923 i915_mmio_reg_offset(tbl->reg) == offset) in find_reg()
947 i915_mmio_reg_offset(reg), a, b); in result_eq()
969 i915_mmio_reg_offset(re in result_neq()
[all...]
H A Dintel_workarounds.c117 unsigned int addr = i915_mmio_reg_offset(wa->reg); in _wa_add()
145 if (i915_mmio_reg_offset(wal->list[mid].reg) < addr) { in _wa_add()
147 } else if (i915_mmio_reg_offset(wal->list[mid].reg) > addr) { in _wa_add()
154 i915_mmio_reg_offset(wa_->reg), in _wa_add()
173 GEM_BUG_ON(i915_mmio_reg_offset(wa_[0].reg) == in _wa_add()
174 i915_mmio_reg_offset(wa_[1].reg)); in _wa_add()
175 if (i915_mmio_reg_offset(wa_[1].reg) > in _wa_add()
176 i915_mmio_reg_offset(wa_[0].reg)) in _wa_add()
749 *cs++ = i915_mmio_reg_offset(wa->reg); in intel_engine_emit_ctx_wa()
1336 name, from, i915_mmio_reg_offset(w in wa_verify()
[all...]
H A Dintel_ring_submission.c634 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine->mmio_base)); in load_pd_dir()
638 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
643 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine->mmio_base)); in load_pd_dir()
648 *cs++ = i915_mmio_reg_offset(RING_INSTPM(engine->mmio_base)); in load_pd_dir()
696 *cs++ = i915_mmio_reg_offset( in mi_set_context()
751 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
758 *cs++ = i915_mmio_reg_offset(last_reg); in mi_set_context()
792 *cs++ = i915_mmio_reg_offset(GEN7_L3LOG(slice, i)); in remap_l3_slice()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_perf.c1618 *cs++ = i915_mmio_reg_offset(reg) + 4 * d; in save_restore_register()
1689 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4; in alloc_noa_wait()
1692 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1693 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)); in alloc_noa_wait()
1707 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4; in alloc_noa_wait()
1710 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base)); in alloc_noa_wait()
1711 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)); in alloc_noa_wait()
1730 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE)); in alloc_noa_wait()
1731 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1); in alloc_noa_wait()
1749 *cs++ = i915_mmio_reg_offset(CS_GP in alloc_noa_wait()
[all...]
H A Dintel_uncore.h272 return read##s__(uncore->regs + i915_mmio_reg_offset(reg)); \
279 write##s__(val, uncore->regs + i915_mmio_reg_offset(reg)); \
421 readl(base + i915_mmio_reg_offset(reg))
423 writel(value, base + i915_mmio_reg_offset(reg))
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_dsb.c128 if (reg_val != i915_mmio_reg_offset(reg)) { in intel_dsb_indexed_reg_write()
140 i915_mmio_reg_offset(reg); in intel_dsb_indexed_reg_write()
193 i915_mmio_reg_offset(reg); in intel_dsb_reg_write()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/
H A Dintel_dsb.c127 return prev_opcode == opcode && prev_reg == i915_mmio_reg_offset(reg); in intel_dsb_prev_ins_is_write()
173 i915_mmio_reg_offset(reg)); in intel_dsb_reg_write()
187 i915_mmio_reg_offset(reg); in intel_dsb_reg_write()

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