Searched refs:i0 (Results 1 - 25 of 98) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H A D	mdp5.xml.h	265 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument 267 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument 287 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument 289 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument 319 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC() argument 321 REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) REG_MDP5_IGC_LUT() argument 323 REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) REG_MDP5_IGC_LUT_REG() argument 360 REG_MDP5_CTL(uint32_t i0) REG_MDP5_CTL() argument 374 REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER() argument 376 REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_REG() argument 440 REG_MDP5_CTL_OP(uint32_t i0) REG_MDP5_CTL_OP() argument 462 REG_MDP5_CTL_FLUSH(uint32_t i0) REG_MDP5_CTL_FLUSH() argument 493 REG_MDP5_CTL_START(uint32_t i0) REG_MDP5_CTL_START() argument 495 REG_MDP5_CTL_PACK_3D(uint32_t i0) REG_MDP5_CTL_PACK_3D() argument 509 REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT() argument 511 REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT_REG() argument 554 REG_MDP5_PIPE(enum mdp5_pipe i0) REG_MDP5_PIPE() argument 556 REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) REG_MDP5_PIPE_OP_MODE() argument 571 REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_CTL_BASE() argument 573 REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_LUT_BASE() argument 575 REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_LUT_SWAP() argument 577 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument 591 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument 605 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument 619 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument 633 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument 641 REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument 643 REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument 657 REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument 659 REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument 673 REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument 675 REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument 683 REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS() argument 685 REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument 693 REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_SIZE() argument 707 REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_IMG_SIZE() argument 721 REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_XY() argument 735 REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_OUT_SIZE() argument 749 REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) REG_MDP5_PIPE_OUT_XY() argument 763 REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC0_ADDR() argument 765 REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC1_ADDR() argument 767 REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC2_ADDR() argument 769 REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC3_ADDR() argument 771 REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_STRIDE_A() argument 785 REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_STRIDE_B() argument 799 REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_STILE_FRAME_SIZE() argument 801 REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_FORMAT() argument 855 REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_UNPACK() argument 881 REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_OP_MODE() argument 898 REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument 900 REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) REG_MDP5_PIPE_FETCH_CONFIG() argument 902 REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) REG_MDP5_PIPE_VC1_RANGE() argument 904 REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument 906 REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument 908 REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument 910 REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument 912 REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument 914 REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument 916 REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument 918 REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument 920 REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) REG_MDP5_PIPE_DECIMATION() argument 943 REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT() argument 945 REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_LR() argument 971 REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_TB() argument 997 REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument 1011 REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CONFIG() argument 1051 REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument 1053 REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument 1055 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument 1057 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument 1059 REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument 1061 REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument 1075 REG_MDP5_LM(uint32_t i0) REG_MDP5_LM() argument 1077 REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) REG_MDP5_LM_BLEND_COLOR_OUT() argument 1087 REG_MDP5_LM_OUT_SIZE(uint32_t i0) REG_MDP5_LM_OUT_SIZE() argument 1101 REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) REG_MDP5_LM_BORDER_COLOR_0() argument 1103 REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) REG_MDP5_LM_BORDER_COLOR_1() argument 1118 REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND() argument 1120 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_OP_MODE() argument 1142 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_ALPHA() argument 1144 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_ALPHA() argument 1146 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument 1148 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument 1150 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument 1152 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument 1154 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument 1156 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument 1158 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument 1160 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument 1162 REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) REG_MDP5_LM_CURSOR_IMG_SIZE() argument 1176 REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) REG_MDP5_LM_CURSOR_SIZE() argument 1190 REG_MDP5_LM_CURSOR_XY(uint32_t i0) REG_MDP5_LM_CURSOR_XY() argument 1204 REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) REG_MDP5_LM_CURSOR_STRIDE() argument 1212 REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) REG_MDP5_LM_CURSOR_FORMAT() argument 1220 REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) REG_MDP5_LM_CURSOR_BASE_ADDR() argument 1222 REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) REG_MDP5_LM_CURSOR_START_XY() argument 1236 REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument 1246 REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_PARAM() argument 1248 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument 1250 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument 1252 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument 1254 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument 1256 REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) REG_MDP5_LM_GC_LUT_BASE() argument 1268 REG_MDP5_DSPP(uint32_t i0) REG_MDP5_DSPP() argument 1270 REG_MDP5_DSPP_OP_MODE(uint32_t i0) REG_MDP5_DSPP_OP_MODE() argument 1287 REG_MDP5_DSPP_PCC_BASE(uint32_t i0) REG_MDP5_DSPP_PCC_BASE() argument 1289 REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) REG_MDP5_DSPP_DITHER_DEPTH() argument 1291 REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) REG_MDP5_DSPP_HIST_CTL_BASE() argument 1293 REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) REG_MDP5_DSPP_HIST_LUT_BASE() argument 1295 REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) REG_MDP5_DSPP_HIST_LUT_SWAP() argument 1297 REG_MDP5_DSPP_PA_BASE(uint32_t i0) REG_MDP5_DSPP_PA_BASE() argument 1299 REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) REG_MDP5_DSPP_GAMUT_BASE() argument 1301 REG_MDP5_DSPP_GC_BASE(uint32_t i0) REG_MDP5_DSPP_GC_BASE() argument 1313 REG_MDP5_PP(uint32_t i0) REG_MDP5_PP() argument 1315 REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) REG_MDP5_PP_TEAR_CHECK_EN() argument 1317 REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument 1327 REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument 1329 REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) REG_MDP5_PP_SYNC_WRCOUNT() argument 1343 REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) REG_MDP5_PP_VSYNC_INIT_VAL() argument 1345 REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) REG_MDP5_PP_INT_COUNT_VAL() argument 1359 REG_MDP5_PP_SYNC_THRESH(uint32_t i0) REG_MDP5_PP_SYNC_THRESH() argument 1373 REG_MDP5_PP_START_POS(uint32_t i0) REG_MDP5_PP_START_POS() argument 1375 REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) REG_MDP5_PP_RD_PTR_IRQ() argument 1377 REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) REG_MDP5_PP_WR_PTR_IRQ() argument 1379 REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) REG_MDP5_PP_OUT_LINE_COUNT() argument 1381 REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) REG_MDP5_PP_PP_LINE_COUNT() argument 1383 REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) REG_MDP5_PP_AUTOREFRESH_CONFIG() argument 1385 REG_MDP5_PP_FBC_MODE(uint32_t i0) REG_MDP5_PP_FBC_MODE() argument 1387 REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) REG_MDP5_PP_FBC_BUDGET_CTL() argument 1389 REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) REG_MDP5_PP_FBC_LOSSY_MODE() argument 1404 REG_MDP5_WB(uint32_t i0) REG_MDP5_WB() argument 1406 REG_MDP5_WB_DST_FORMAT(uint32_t i0) REG_MDP5_WB_DST_FORMAT() argument 1473 REG_MDP5_WB_DST_OP_MODE(uint32_t i0) REG_MDP5_WB_DST_OP_MODE() argument 1527 REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) REG_MDP5_WB_DST_PACK_PATTERN() argument 1553 REG_MDP5_WB_DST0_ADDR(uint32_t i0) REG_MDP5_WB_DST0_ADDR() argument 1555 REG_MDP5_WB_DST1_ADDR(uint32_t i0) REG_MDP5_WB_DST1_ADDR() argument 1557 REG_MDP5_WB_DST2_ADDR(uint32_t i0) REG_MDP5_WB_DST2_ADDR() argument 1559 REG_MDP5_WB_DST3_ADDR(uint32_t i0) REG_MDP5_WB_DST3_ADDR() argument 1561 REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) REG_MDP5_WB_DST_YSTRIDE0() argument 1575 REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) REG_MDP5_WB_DST_YSTRIDE1() argument 1589 REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) REG_MDP5_WB_DST_DITHER_BITDEPTH() argument 1591 REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW0() argument 1593 REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW1() argument 1595 REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW2() argument 1597 REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW3() argument 1599 REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) REG_MDP5_WB_DST_WRITE_CONFIG() argument 1601 REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) REG_MDP5_WB_ROTATION_DNSCALER() argument 1603 REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_X_0_3() argument 1605 REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_X_1_2() argument 1607 REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_Y_0_3() argument 1609 REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_Y_1_2() argument 1611 REG_MDP5_WB_OUT_SIZE(uint32_t i0) REG_MDP5_WB_OUT_SIZE() argument 1625 REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) REG_MDP5_WB_ALPHA_X_VALUE() argument 1627 REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_0() argument 1641 REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_1() argument 1655 REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_2() argument 1669 REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_3() argument 1683 REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_4() argument 1691 REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP() argument 1693 REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument 1707 REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument 1709 REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument 1723 REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS() argument 1725 REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument 1733 REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS() argument 1735 REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument 1754 REG_MDP5_INTF(uint32_t i0) REG_MDP5_INTF() argument 1756 REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) REG_MDP5_INTF_TIMING_ENGINE_EN() argument 1758 REG_MDP5_INTF_CONFIG(uint32_t i0) REG_MDP5_INTF_CONFIG() argument 1760 REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) REG_MDP5_INTF_HSYNC_CTL() argument 1774 REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) REG_MDP5_INTF_VSYNC_PERIOD_F0() argument 1776 REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) REG_MDP5_INTF_VSYNC_PERIOD_F1() argument 1778 REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) REG_MDP5_INTF_VSYNC_LEN_F0() argument 1780 REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) REG_MDP5_INTF_VSYNC_LEN_F1() argument 1782 REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) REG_MDP5_INTF_DISPLAY_VSTART_F0() argument 1784 REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) REG_MDP5_INTF_DISPLAY_VSTART_F1() argument 1786 REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) REG_MDP5_INTF_DISPLAY_VEND_F0() argument 1788 REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) REG_MDP5_INTF_DISPLAY_VEND_F1() argument 1790 REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) REG_MDP5_INTF_ACTIVE_VSTART_F0() argument 1799 REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) REG_MDP5_INTF_ACTIVE_VSTART_F1() argument 1807 REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) REG_MDP5_INTF_ACTIVE_VEND_F0() argument 1809 REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) REG_MDP5_INTF_ACTIVE_VEND_F1() argument 1811 REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) REG_MDP5_INTF_DISPLAY_HCTL() argument 1825 REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) REG_MDP5_INTF_ACTIVE_HCTL() argument 1840 REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) REG_MDP5_INTF_BORDER_COLOR() argument 1842 REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) REG_MDP5_INTF_UNDERFLOW_COLOR() argument 1844 REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) REG_MDP5_INTF_HSYNC_SKEW() argument 1846 REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) REG_MDP5_INTF_POLARITY_CTL() argument 1851 REG_MDP5_INTF_TEST_CTL(uint32_t i0) REG_MDP5_INTF_TEST_CTL() argument 1853 REG_MDP5_INTF_TP_COLOR0(uint32_t i0) REG_MDP5_INTF_TP_COLOR0() argument 1855 REG_MDP5_INTF_TP_COLOR1(uint32_t i0) REG_MDP5_INTF_TP_COLOR1() argument 1857 REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument 1859 REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) REG_MDP5_INTF_PANEL_FORMAT() argument 1861 REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument 1863 REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) REG_MDP5_INTF_FRAME_COUNT() argument 1865 REG_MDP5_INTF_LINE_COUNT(uint32_t i0) REG_MDP5_INTF_LINE_COUNT() argument 1867 REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) REG_MDP5_INTF_DEFLICKER_CONFIG() argument 1869 REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument 1871 REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument 1873 REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) REG_MDP5_INTF_TPG_ENABLE() argument 1875 REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) REG_MDP5_INTF_TPG_MAIN_CONTROL() argument 1877 REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument 1879 REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument 1881 REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) REG_MDP5_INTF_TPG_RECTANGLE() argument 1883 REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) REG_MDP5_INTF_TPG_INITIAL_VALUE() argument 1885 REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument 1887 REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) REG_MDP5_INTF_TPG_RGB_MAPPING() argument 1897 REG_MDP5_AD(uint32_t i0) REG_MDP5_AD() argument 1899 REG_MDP5_AD_BYPASS(uint32_t i0) REG_MDP5_AD_BYPASS() argument 1901 REG_MDP5_AD_CTRL_0(uint32_t i0) REG_MDP5_AD_CTRL_0() argument 1903 REG_MDP5_AD_CTRL_1(uint32_t i0) REG_MDP5_AD_CTRL_1() argument 1905 REG_MDP5_AD_FRAME_SIZE(uint32_t i0) REG_MDP5_AD_FRAME_SIZE() argument 1907 REG_MDP5_AD_CON_CTRL_0(uint32_t i0) REG_MDP5_AD_CON_CTRL_0() argument 1909 REG_MDP5_AD_CON_CTRL_1(uint32_t i0) REG_MDP5_AD_CON_CTRL_1() argument 1911 REG_MDP5_AD_STR_MAN(uint32_t i0) REG_MDP5_AD_STR_MAN() argument 1913 REG_MDP5_AD_VAR(uint32_t i0) REG_MDP5_AD_VAR() argument 1915 REG_MDP5_AD_DITH(uint32_t i0) REG_MDP5_AD_DITH() argument 1917 REG_MDP5_AD_DITH_CTRL(uint32_t i0) REG_MDP5_AD_DITH_CTRL() argument 1919 REG_MDP5_AD_AMP_LIM(uint32_t i0) REG_MDP5_AD_AMP_LIM() argument 1921 REG_MDP5_AD_SLOPE(uint32_t i0) REG_MDP5_AD_SLOPE() argument 1923 REG_MDP5_AD_BW_LVL(uint32_t i0) REG_MDP5_AD_BW_LVL() argument 1925 REG_MDP5_AD_LOGO_POS(uint32_t i0) REG_MDP5_AD_LOGO_POS() argument 1927 REG_MDP5_AD_LUT_FI(uint32_t i0) REG_MDP5_AD_LUT_FI() argument 1929 REG_MDP5_AD_LUT_CC(uint32_t i0) REG_MDP5_AD_LUT_CC() argument 1931 REG_MDP5_AD_STR_LIM(uint32_t i0) REG_MDP5_AD_STR_LIM() argument 1933 REG_MDP5_AD_CALIB_AB(uint32_t i0) REG_MDP5_AD_CALIB_AB() argument 1935 REG_MDP5_AD_CALIB_CD(uint32_t i0) REG_MDP5_AD_CALIB_CD() argument 1937 REG_MDP5_AD_MODE_SEL(uint32_t i0) REG_MDP5_AD_MODE_SEL() argument 1939 REG_MDP5_AD_TFILT_CTRL(uint32_t i0) REG_MDP5_AD_TFILT_CTRL() argument 1941 REG_MDP5_AD_BL_MINMAX(uint32_t i0) REG_MDP5_AD_BL_MINMAX() argument 1943 REG_MDP5_AD_BL(uint32_t i0) REG_MDP5_AD_BL() argument 1945 REG_MDP5_AD_BL_MAX(uint32_t i0) REG_MDP5_AD_BL_MAX() argument 1947 REG_MDP5_AD_AL(uint32_t i0) REG_MDP5_AD_AL() argument 1949 REG_MDP5_AD_AL_MIN(uint32_t i0) REG_MDP5_AD_AL_MIN() argument 1951 REG_MDP5_AD_AL_FILT(uint32_t i0) REG_MDP5_AD_AL_FILT() argument 1953 REG_MDP5_AD_CFG_BUF(uint32_t i0) REG_MDP5_AD_CFG_BUF() argument 1955 REG_MDP5_AD_LUT_AL(uint32_t i0) REG_MDP5_AD_LUT_AL() argument 1957 REG_MDP5_AD_TARG_STR(uint32_t i0) REG_MDP5_AD_TARG_STR() argument 1959 REG_MDP5_AD_START_CALC(uint32_t i0) REG_MDP5_AD_START_CALC() argument 1961 REG_MDP5_AD_STR_OUT(uint32_t i0) REG_MDP5_AD_STR_OUT() argument 1963 REG_MDP5_AD_BL_OUT(uint32_t i0) REG_MDP5_AD_BL_OUT() argument 1965 REG_MDP5_AD_CALC_DONE(uint32_t i0) REG_MDP5_AD_CALC_DONE() argument [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A D	mdp5.xml.h	276 static inline uint32_t REG_MDP5_SMP_ALLOC_W(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W() argument 278 static inline uint32_t REG_MDP5_SMP_ALLOC_W_REG(uint32_t i0) { return 0x00000080 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_W_REG() argument 298 static inline uint32_t REG_MDP5_SMP_ALLOC_R(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R() argument 300 static inline uint32_t REG_MDP5_SMP_ALLOC_R_REG(uint32_t i0) { return 0x00000130 + 0x4*i0; } in REG_MDP5_SMP_ALLOC_R_REG() argument 330 static inline uint32_t REG_MDP5_IGC(enum mdp5_igc_type i0) { return 0x00000000 + __offset_IGC(i0); } in REG_MDP5_IGC() argument 332 REG_MDP5_IGC_LUT(enum mdp5_igc_type i0, uint32_t i1) REG_MDP5_IGC_LUT() argument 334 REG_MDP5_IGC_LUT_REG(enum mdp5_igc_type i0, uint32_t i1) REG_MDP5_IGC_LUT_REG() argument 371 REG_MDP5_CTL(uint32_t i0) REG_MDP5_CTL() argument 385 REG_MDP5_CTL_LAYER(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER() argument 387 REG_MDP5_CTL_LAYER_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_REG() argument 451 REG_MDP5_CTL_OP(uint32_t i0) REG_MDP5_CTL_OP() argument 473 REG_MDP5_CTL_FLUSH(uint32_t i0) REG_MDP5_CTL_FLUSH() argument 504 REG_MDP5_CTL_START(uint32_t i0) REG_MDP5_CTL_START() argument 506 REG_MDP5_CTL_PACK_3D(uint32_t i0) REG_MDP5_CTL_PACK_3D() argument 520 REG_MDP5_CTL_LAYER_EXT(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT() argument 522 REG_MDP5_CTL_LAYER_EXT_REG(uint32_t i0, uint32_t i1) REG_MDP5_CTL_LAYER_EXT_REG() argument 565 REG_MDP5_PIPE(enum mdp5_pipe i0) REG_MDP5_PIPE() argument 567 REG_MDP5_PIPE_OP_MODE(enum mdp5_pipe i0) REG_MDP5_PIPE_OP_MODE() argument 582 REG_MDP5_PIPE_HIST_CTL_BASE(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_CTL_BASE() argument 584 REG_MDP5_PIPE_HIST_LUT_BASE(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_LUT_BASE() argument 586 REG_MDP5_PIPE_HIST_LUT_SWAP(enum mdp5_pipe i0) REG_MDP5_PIPE_HIST_LUT_SWAP() argument 588 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_0() argument 602 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_1() argument 616 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_2() argument 630 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_3() argument 644 REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4(enum mdp5_pipe i0) REG_MDP5_PIPE_CSC_1_MATRIX_COEFF_4() argument 652 REG_MDP5_PIPE_CSC_1_PRE_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP() argument 654 REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_CLAMP_REG() argument 668 REG_MDP5_PIPE_CSC_1_POST_CLAMP(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP() argument 670 REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_CLAMP_REG() argument 684 REG_MDP5_PIPE_CSC_1_PRE_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS() argument 686 REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_PRE_BIAS_REG() argument 694 REG_MDP5_PIPE_CSC_1_POST_BIAS(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS() argument 696 REG_MDP5_PIPE_CSC_1_POST_BIAS_REG(enum mdp5_pipe i0, uint32_t i1) REG_MDP5_PIPE_CSC_1_POST_BIAS_REG() argument 704 REG_MDP5_PIPE_SRC_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_SIZE() argument 718 REG_MDP5_PIPE_SRC_IMG_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_IMG_SIZE() argument 732 REG_MDP5_PIPE_SRC_XY(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_XY() argument 746 REG_MDP5_PIPE_OUT_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_OUT_SIZE() argument 760 REG_MDP5_PIPE_OUT_XY(enum mdp5_pipe i0) REG_MDP5_PIPE_OUT_XY() argument 774 REG_MDP5_PIPE_SRC0_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC0_ADDR() argument 776 REG_MDP5_PIPE_SRC1_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC1_ADDR() argument 778 REG_MDP5_PIPE_SRC2_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC2_ADDR() argument 780 REG_MDP5_PIPE_SRC3_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC3_ADDR() argument 782 REG_MDP5_PIPE_SRC_STRIDE_A(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_STRIDE_A() argument 796 REG_MDP5_PIPE_SRC_STRIDE_B(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_STRIDE_B() argument 810 REG_MDP5_PIPE_STILE_FRAME_SIZE(enum mdp5_pipe i0) REG_MDP5_PIPE_STILE_FRAME_SIZE() argument 812 REG_MDP5_PIPE_SRC_FORMAT(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_FORMAT() argument 866 REG_MDP5_PIPE_SRC_UNPACK(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_UNPACK() argument 892 REG_MDP5_PIPE_SRC_OP_MODE(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_OP_MODE() argument 909 REG_MDP5_PIPE_SRC_CONSTANT_COLOR(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_CONSTANT_COLOR() argument 911 REG_MDP5_PIPE_FETCH_CONFIG(enum mdp5_pipe i0) REG_MDP5_PIPE_FETCH_CONFIG() argument 913 REG_MDP5_PIPE_VC1_RANGE(enum mdp5_pipe i0) REG_MDP5_PIPE_VC1_RANGE() argument 915 REG_MDP5_PIPE_REQPRIO_FIFO_WM_0(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_0() argument 917 REG_MDP5_PIPE_REQPRIO_FIFO_WM_1(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_1() argument 919 REG_MDP5_PIPE_REQPRIO_FIFO_WM_2(enum mdp5_pipe i0) REG_MDP5_PIPE_REQPRIO_FIFO_WM_2() argument 921 REG_MDP5_PIPE_SRC_ADDR_SW_STATUS(enum mdp5_pipe i0) REG_MDP5_PIPE_SRC_ADDR_SW_STATUS() argument 923 REG_MDP5_PIPE_CURRENT_SRC0_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC0_ADDR() argument 925 REG_MDP5_PIPE_CURRENT_SRC1_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC1_ADDR() argument 927 REG_MDP5_PIPE_CURRENT_SRC2_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC2_ADDR() argument 929 REG_MDP5_PIPE_CURRENT_SRC3_ADDR(enum mdp5_pipe i0) REG_MDP5_PIPE_CURRENT_SRC3_ADDR() argument 931 REG_MDP5_PIPE_DECIMATION(enum mdp5_pipe i0) REG_MDP5_PIPE_DECIMATION() argument 954 REG_MDP5_PIPE_SW_PIX_EXT(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT() argument 956 REG_MDP5_PIPE_SW_PIX_EXT_LR(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_LR() argument 982 REG_MDP5_PIPE_SW_PIX_EXT_TB(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_TB() argument 1008 REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS(enum mdp5_pipe i0, enum mdp_component_type i1) REG_MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS() argument 1022 REG_MDP5_PIPE_SCALE_CONFIG(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CONFIG() argument 1062 REG_MDP5_PIPE_SCALE_PHASE_STEP_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_PHASE_STEP_X() argument 1064 REG_MDP5_PIPE_SCALE_PHASE_STEP_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_PHASE_STEP_Y() argument 1066 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_X() argument 1068 REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_CR_PHASE_STEP_Y() argument 1070 REG_MDP5_PIPE_SCALE_INIT_PHASE_X(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_INIT_PHASE_X() argument 1072 REG_MDP5_PIPE_SCALE_INIT_PHASE_Y(enum mdp5_pipe i0) REG_MDP5_PIPE_SCALE_INIT_PHASE_Y() argument 1086 REG_MDP5_LM(uint32_t i0) REG_MDP5_LM() argument 1088 REG_MDP5_LM_BLEND_COLOR_OUT(uint32_t i0) REG_MDP5_LM_BLEND_COLOR_OUT() argument 1098 REG_MDP5_LM_OUT_SIZE(uint32_t i0) REG_MDP5_LM_OUT_SIZE() argument 1112 REG_MDP5_LM_BORDER_COLOR_0(uint32_t i0) REG_MDP5_LM_BORDER_COLOR_0() argument 1114 REG_MDP5_LM_BORDER_COLOR_1(uint32_t i0) REG_MDP5_LM_BORDER_COLOR_1() argument 1129 REG_MDP5_LM_BLEND(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND() argument 1131 REG_MDP5_LM_BLEND_OP_MODE(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_OP_MODE() argument 1153 REG_MDP5_LM_BLEND_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_ALPHA() argument 1155 REG_MDP5_LM_BLEND_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_ALPHA() argument 1157 REG_MDP5_LM_BLEND_FG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW0() argument 1159 REG_MDP5_LM_BLEND_FG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_LOW1() argument 1161 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH0() argument 1163 REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_FG_TRANSP_HIGH1() argument 1165 REG_MDP5_LM_BLEND_BG_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW0() argument 1167 REG_MDP5_LM_BLEND_BG_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_LOW1() argument 1169 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH0() argument 1171 REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP5_LM_BLEND_BG_TRANSP_HIGH1() argument 1173 REG_MDP5_LM_CURSOR_IMG_SIZE(uint32_t i0) REG_MDP5_LM_CURSOR_IMG_SIZE() argument 1187 REG_MDP5_LM_CURSOR_SIZE(uint32_t i0) REG_MDP5_LM_CURSOR_SIZE() argument 1201 REG_MDP5_LM_CURSOR_XY(uint32_t i0) REG_MDP5_LM_CURSOR_XY() argument 1215 REG_MDP5_LM_CURSOR_STRIDE(uint32_t i0) REG_MDP5_LM_CURSOR_STRIDE() argument 1223 REG_MDP5_LM_CURSOR_FORMAT(uint32_t i0) REG_MDP5_LM_CURSOR_FORMAT() argument 1231 REG_MDP5_LM_CURSOR_BASE_ADDR(uint32_t i0) REG_MDP5_LM_CURSOR_BASE_ADDR() argument 1233 REG_MDP5_LM_CURSOR_START_XY(uint32_t i0) REG_MDP5_LM_CURSOR_START_XY() argument 1247 REG_MDP5_LM_CURSOR_BLEND_CONFIG(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_CONFIG() argument 1257 REG_MDP5_LM_CURSOR_BLEND_PARAM(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_PARAM() argument 1259 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW0() argument 1261 REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_LOW1() argument 1263 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH0() argument 1265 REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1(uint32_t i0) REG_MDP5_LM_CURSOR_BLEND_TRANSP_HIGH1() argument 1267 REG_MDP5_LM_GC_LUT_BASE(uint32_t i0) REG_MDP5_LM_GC_LUT_BASE() argument 1279 REG_MDP5_DSPP(uint32_t i0) REG_MDP5_DSPP() argument 1281 REG_MDP5_DSPP_OP_MODE(uint32_t i0) REG_MDP5_DSPP_OP_MODE() argument 1298 REG_MDP5_DSPP_PCC_BASE(uint32_t i0) REG_MDP5_DSPP_PCC_BASE() argument 1300 REG_MDP5_DSPP_DITHER_DEPTH(uint32_t i0) REG_MDP5_DSPP_DITHER_DEPTH() argument 1302 REG_MDP5_DSPP_HIST_CTL_BASE(uint32_t i0) REG_MDP5_DSPP_HIST_CTL_BASE() argument 1304 REG_MDP5_DSPP_HIST_LUT_BASE(uint32_t i0) REG_MDP5_DSPP_HIST_LUT_BASE() argument 1306 REG_MDP5_DSPP_HIST_LUT_SWAP(uint32_t i0) REG_MDP5_DSPP_HIST_LUT_SWAP() argument 1308 REG_MDP5_DSPP_PA_BASE(uint32_t i0) REG_MDP5_DSPP_PA_BASE() argument 1310 REG_MDP5_DSPP_GAMUT_BASE(uint32_t i0) REG_MDP5_DSPP_GAMUT_BASE() argument 1312 REG_MDP5_DSPP_GC_BASE(uint32_t i0) REG_MDP5_DSPP_GC_BASE() argument 1324 REG_MDP5_PP(uint32_t i0) REG_MDP5_PP() argument 1326 REG_MDP5_PP_TEAR_CHECK_EN(uint32_t i0) REG_MDP5_PP_TEAR_CHECK_EN() argument 1328 REG_MDP5_PP_SYNC_CONFIG_VSYNC(uint32_t i0) REG_MDP5_PP_SYNC_CONFIG_VSYNC() argument 1338 REG_MDP5_PP_SYNC_CONFIG_HEIGHT(uint32_t i0) REG_MDP5_PP_SYNC_CONFIG_HEIGHT() argument 1340 REG_MDP5_PP_SYNC_WRCOUNT(uint32_t i0) REG_MDP5_PP_SYNC_WRCOUNT() argument 1354 REG_MDP5_PP_VSYNC_INIT_VAL(uint32_t i0) REG_MDP5_PP_VSYNC_INIT_VAL() argument 1356 REG_MDP5_PP_INT_COUNT_VAL(uint32_t i0) REG_MDP5_PP_INT_COUNT_VAL() argument 1370 REG_MDP5_PP_SYNC_THRESH(uint32_t i0) REG_MDP5_PP_SYNC_THRESH() argument 1384 REG_MDP5_PP_START_POS(uint32_t i0) REG_MDP5_PP_START_POS() argument 1386 REG_MDP5_PP_RD_PTR_IRQ(uint32_t i0) REG_MDP5_PP_RD_PTR_IRQ() argument 1388 REG_MDP5_PP_WR_PTR_IRQ(uint32_t i0) REG_MDP5_PP_WR_PTR_IRQ() argument 1390 REG_MDP5_PP_OUT_LINE_COUNT(uint32_t i0) REG_MDP5_PP_OUT_LINE_COUNT() argument 1392 REG_MDP5_PP_PP_LINE_COUNT(uint32_t i0) REG_MDP5_PP_PP_LINE_COUNT() argument 1394 REG_MDP5_PP_AUTOREFRESH_CONFIG(uint32_t i0) REG_MDP5_PP_AUTOREFRESH_CONFIG() argument 1396 REG_MDP5_PP_FBC_MODE(uint32_t i0) REG_MDP5_PP_FBC_MODE() argument 1398 REG_MDP5_PP_FBC_BUDGET_CTL(uint32_t i0) REG_MDP5_PP_FBC_BUDGET_CTL() argument 1400 REG_MDP5_PP_FBC_LOSSY_MODE(uint32_t i0) REG_MDP5_PP_FBC_LOSSY_MODE() argument 1415 REG_MDP5_WB(uint32_t i0) REG_MDP5_WB() argument 1417 REG_MDP5_WB_DST_FORMAT(uint32_t i0) REG_MDP5_WB_DST_FORMAT() argument 1484 REG_MDP5_WB_DST_OP_MODE(uint32_t i0) REG_MDP5_WB_DST_OP_MODE() argument 1538 REG_MDP5_WB_DST_PACK_PATTERN(uint32_t i0) REG_MDP5_WB_DST_PACK_PATTERN() argument 1564 REG_MDP5_WB_DST0_ADDR(uint32_t i0) REG_MDP5_WB_DST0_ADDR() argument 1566 REG_MDP5_WB_DST1_ADDR(uint32_t i0) REG_MDP5_WB_DST1_ADDR() argument 1568 REG_MDP5_WB_DST2_ADDR(uint32_t i0) REG_MDP5_WB_DST2_ADDR() argument 1570 REG_MDP5_WB_DST3_ADDR(uint32_t i0) REG_MDP5_WB_DST3_ADDR() argument 1572 REG_MDP5_WB_DST_YSTRIDE0(uint32_t i0) REG_MDP5_WB_DST_YSTRIDE0() argument 1586 REG_MDP5_WB_DST_YSTRIDE1(uint32_t i0) REG_MDP5_WB_DST_YSTRIDE1() argument 1600 REG_MDP5_WB_DST_DITHER_BITDEPTH(uint32_t i0) REG_MDP5_WB_DST_DITHER_BITDEPTH() argument 1602 REG_MDP5_WB_DITHER_MATRIX_ROW0(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW0() argument 1604 REG_MDP5_WB_DITHER_MATRIX_ROW1(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW1() argument 1606 REG_MDP5_WB_DITHER_MATRIX_ROW2(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW2() argument 1608 REG_MDP5_WB_DITHER_MATRIX_ROW3(uint32_t i0) REG_MDP5_WB_DITHER_MATRIX_ROW3() argument 1610 REG_MDP5_WB_DST_WRITE_CONFIG(uint32_t i0) REG_MDP5_WB_DST_WRITE_CONFIG() argument 1612 REG_MDP5_WB_ROTATION_DNSCALER(uint32_t i0) REG_MDP5_WB_ROTATION_DNSCALER() argument 1614 REG_MDP5_WB_N16_INIT_PHASE_X_0_3(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_X_0_3() argument 1616 REG_MDP5_WB_N16_INIT_PHASE_X_1_2(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_X_1_2() argument 1618 REG_MDP5_WB_N16_INIT_PHASE_Y_0_3(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_Y_0_3() argument 1620 REG_MDP5_WB_N16_INIT_PHASE_Y_1_2(uint32_t i0) REG_MDP5_WB_N16_INIT_PHASE_Y_1_2() argument 1622 REG_MDP5_WB_OUT_SIZE(uint32_t i0) REG_MDP5_WB_OUT_SIZE() argument 1636 REG_MDP5_WB_ALPHA_X_VALUE(uint32_t i0) REG_MDP5_WB_ALPHA_X_VALUE() argument 1638 REG_MDP5_WB_CSC_MATRIX_COEFF_0(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_0() argument 1652 REG_MDP5_WB_CSC_MATRIX_COEFF_1(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_1() argument 1666 REG_MDP5_WB_CSC_MATRIX_COEFF_2(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_2() argument 1680 REG_MDP5_WB_CSC_MATRIX_COEFF_3(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_3() argument 1694 REG_MDP5_WB_CSC_MATRIX_COEFF_4(uint32_t i0) REG_MDP5_WB_CSC_MATRIX_COEFF_4() argument 1702 REG_MDP5_WB_CSC_COMP_PRECLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP() argument 1704 REG_MDP5_WB_CSC_COMP_PRECLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PRECLAMP_REG() argument 1718 REG_MDP5_WB_CSC_COMP_POSTCLAMP(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP() argument 1720 REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTCLAMP_REG() argument 1734 REG_MDP5_WB_CSC_COMP_PREBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS() argument 1736 REG_MDP5_WB_CSC_COMP_PREBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_PREBIAS_REG() argument 1744 REG_MDP5_WB_CSC_COMP_POSTBIAS(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS() argument 1746 REG_MDP5_WB_CSC_COMP_POSTBIAS_REG(uint32_t i0, uint32_t i1) REG_MDP5_WB_CSC_COMP_POSTBIAS_REG() argument 1765 REG_MDP5_INTF(uint32_t i0) REG_MDP5_INTF() argument 1767 REG_MDP5_INTF_TIMING_ENGINE_EN(uint32_t i0) REG_MDP5_INTF_TIMING_ENGINE_EN() argument 1769 REG_MDP5_INTF_CONFIG(uint32_t i0) REG_MDP5_INTF_CONFIG() argument 1771 REG_MDP5_INTF_HSYNC_CTL(uint32_t i0) REG_MDP5_INTF_HSYNC_CTL() argument 1785 REG_MDP5_INTF_VSYNC_PERIOD_F0(uint32_t i0) REG_MDP5_INTF_VSYNC_PERIOD_F0() argument 1787 REG_MDP5_INTF_VSYNC_PERIOD_F1(uint32_t i0) REG_MDP5_INTF_VSYNC_PERIOD_F1() argument 1789 REG_MDP5_INTF_VSYNC_LEN_F0(uint32_t i0) REG_MDP5_INTF_VSYNC_LEN_F0() argument 1791 REG_MDP5_INTF_VSYNC_LEN_F1(uint32_t i0) REG_MDP5_INTF_VSYNC_LEN_F1() argument 1793 REG_MDP5_INTF_DISPLAY_VSTART_F0(uint32_t i0) REG_MDP5_INTF_DISPLAY_VSTART_F0() argument 1795 REG_MDP5_INTF_DISPLAY_VSTART_F1(uint32_t i0) REG_MDP5_INTF_DISPLAY_VSTART_F1() argument 1797 REG_MDP5_INTF_DISPLAY_VEND_F0(uint32_t i0) REG_MDP5_INTF_DISPLAY_VEND_F0() argument 1799 REG_MDP5_INTF_DISPLAY_VEND_F1(uint32_t i0) REG_MDP5_INTF_DISPLAY_VEND_F1() argument 1801 REG_MDP5_INTF_ACTIVE_VSTART_F0(uint32_t i0) REG_MDP5_INTF_ACTIVE_VSTART_F0() argument 1810 REG_MDP5_INTF_ACTIVE_VSTART_F1(uint32_t i0) REG_MDP5_INTF_ACTIVE_VSTART_F1() argument 1818 REG_MDP5_INTF_ACTIVE_VEND_F0(uint32_t i0) REG_MDP5_INTF_ACTIVE_VEND_F0() argument 1820 REG_MDP5_INTF_ACTIVE_VEND_F1(uint32_t i0) REG_MDP5_INTF_ACTIVE_VEND_F1() argument 1822 REG_MDP5_INTF_DISPLAY_HCTL(uint32_t i0) REG_MDP5_INTF_DISPLAY_HCTL() argument 1836 REG_MDP5_INTF_ACTIVE_HCTL(uint32_t i0) REG_MDP5_INTF_ACTIVE_HCTL() argument 1851 REG_MDP5_INTF_BORDER_COLOR(uint32_t i0) REG_MDP5_INTF_BORDER_COLOR() argument 1853 REG_MDP5_INTF_UNDERFLOW_COLOR(uint32_t i0) REG_MDP5_INTF_UNDERFLOW_COLOR() argument 1855 REG_MDP5_INTF_HSYNC_SKEW(uint32_t i0) REG_MDP5_INTF_HSYNC_SKEW() argument 1857 REG_MDP5_INTF_POLARITY_CTL(uint32_t i0) REG_MDP5_INTF_POLARITY_CTL() argument 1862 REG_MDP5_INTF_TEST_CTL(uint32_t i0) REG_MDP5_INTF_TEST_CTL() argument 1864 REG_MDP5_INTF_TP_COLOR0(uint32_t i0) REG_MDP5_INTF_TP_COLOR0() argument 1866 REG_MDP5_INTF_TP_COLOR1(uint32_t i0) REG_MDP5_INTF_TP_COLOR1() argument 1868 REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN(uint32_t i0) REG_MDP5_INTF_DSI_CMD_MODE_TRIGGER_EN() argument 1870 REG_MDP5_INTF_PANEL_FORMAT(uint32_t i0) REG_MDP5_INTF_PANEL_FORMAT() argument 1872 REG_MDP5_INTF_FRAME_LINE_COUNT_EN(uint32_t i0) REG_MDP5_INTF_FRAME_LINE_COUNT_EN() argument 1874 REG_MDP5_INTF_FRAME_COUNT(uint32_t i0) REG_MDP5_INTF_FRAME_COUNT() argument 1876 REG_MDP5_INTF_LINE_COUNT(uint32_t i0) REG_MDP5_INTF_LINE_COUNT() argument 1878 REG_MDP5_INTF_DEFLICKER_CONFIG(uint32_t i0) REG_MDP5_INTF_DEFLICKER_CONFIG() argument 1880 REG_MDP5_INTF_DEFLICKER_STRNG_COEFF(uint32_t i0) REG_MDP5_INTF_DEFLICKER_STRNG_COEFF() argument 1882 REG_MDP5_INTF_DEFLICKER_WEAK_COEFF(uint32_t i0) REG_MDP5_INTF_DEFLICKER_WEAK_COEFF() argument 1884 REG_MDP5_INTF_TPG_ENABLE(uint32_t i0) REG_MDP5_INTF_TPG_ENABLE() argument 1886 REG_MDP5_INTF_TPG_MAIN_CONTROL(uint32_t i0) REG_MDP5_INTF_TPG_MAIN_CONTROL() argument 1888 REG_MDP5_INTF_TPG_VIDEO_CONFIG(uint32_t i0) REG_MDP5_INTF_TPG_VIDEO_CONFIG() argument 1890 REG_MDP5_INTF_TPG_COMPONENT_LIMITS(uint32_t i0) REG_MDP5_INTF_TPG_COMPONENT_LIMITS() argument 1892 REG_MDP5_INTF_TPG_RECTANGLE(uint32_t i0) REG_MDP5_INTF_TPG_RECTANGLE() argument 1894 REG_MDP5_INTF_TPG_INITIAL_VALUE(uint32_t i0) REG_MDP5_INTF_TPG_INITIAL_VALUE() argument 1896 REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME(uint32_t i0) REG_MDP5_INTF_TPG_BLK_WHITE_PATTERN_FRAME() argument 1898 REG_MDP5_INTF_TPG_RGB_MAPPING(uint32_t i0) REG_MDP5_INTF_TPG_RGB_MAPPING() argument 1908 REG_MDP5_AD(uint32_t i0) REG_MDP5_AD() argument 1910 REG_MDP5_AD_BYPASS(uint32_t i0) REG_MDP5_AD_BYPASS() argument 1912 REG_MDP5_AD_CTRL_0(uint32_t i0) REG_MDP5_AD_CTRL_0() argument 1914 REG_MDP5_AD_CTRL_1(uint32_t i0) REG_MDP5_AD_CTRL_1() argument 1916 REG_MDP5_AD_FRAME_SIZE(uint32_t i0) REG_MDP5_AD_FRAME_SIZE() argument 1918 REG_MDP5_AD_CON_CTRL_0(uint32_t i0) REG_MDP5_AD_CON_CTRL_0() argument 1920 REG_MDP5_AD_CON_CTRL_1(uint32_t i0) REG_MDP5_AD_CON_CTRL_1() argument 1922 REG_MDP5_AD_STR_MAN(uint32_t i0) REG_MDP5_AD_STR_MAN() argument 1924 REG_MDP5_AD_VAR(uint32_t i0) REG_MDP5_AD_VAR() argument 1926 REG_MDP5_AD_DITH(uint32_t i0) REG_MDP5_AD_DITH() argument 1928 REG_MDP5_AD_DITH_CTRL(uint32_t i0) REG_MDP5_AD_DITH_CTRL() argument 1930 REG_MDP5_AD_AMP_LIM(uint32_t i0) REG_MDP5_AD_AMP_LIM() argument 1932 REG_MDP5_AD_SLOPE(uint32_t i0) REG_MDP5_AD_SLOPE() argument 1934 REG_MDP5_AD_BW_LVL(uint32_t i0) REG_MDP5_AD_BW_LVL() argument 1936 REG_MDP5_AD_LOGO_POS(uint32_t i0) REG_MDP5_AD_LOGO_POS() argument 1938 REG_MDP5_AD_LUT_FI(uint32_t i0) REG_MDP5_AD_LUT_FI() argument 1940 REG_MDP5_AD_LUT_CC(uint32_t i0) REG_MDP5_AD_LUT_CC() argument 1942 REG_MDP5_AD_STR_LIM(uint32_t i0) REG_MDP5_AD_STR_LIM() argument 1944 REG_MDP5_AD_CALIB_AB(uint32_t i0) REG_MDP5_AD_CALIB_AB() argument 1946 REG_MDP5_AD_CALIB_CD(uint32_t i0) REG_MDP5_AD_CALIB_CD() argument 1948 REG_MDP5_AD_MODE_SEL(uint32_t i0) REG_MDP5_AD_MODE_SEL() argument 1950 REG_MDP5_AD_TFILT_CTRL(uint32_t i0) REG_MDP5_AD_TFILT_CTRL() argument 1952 REG_MDP5_AD_BL_MINMAX(uint32_t i0) REG_MDP5_AD_BL_MINMAX() argument 1954 REG_MDP5_AD_BL(uint32_t i0) REG_MDP5_AD_BL() argument 1956 REG_MDP5_AD_BL_MAX(uint32_t i0) REG_MDP5_AD_BL_MAX() argument 1958 REG_MDP5_AD_AL(uint32_t i0) REG_MDP5_AD_AL() argument 1960 REG_MDP5_AD_AL_MIN(uint32_t i0) REG_MDP5_AD_AL_MIN() argument 1962 REG_MDP5_AD_AL_FILT(uint32_t i0) REG_MDP5_AD_AL_FILT() argument 1964 REG_MDP5_AD_CFG_BUF(uint32_t i0) REG_MDP5_AD_CFG_BUF() argument 1966 REG_MDP5_AD_LUT_AL(uint32_t i0) REG_MDP5_AD_LUT_AL() argument 1968 REG_MDP5_AD_TARG_STR(uint32_t i0) REG_MDP5_AD_TARG_STR() argument 1970 REG_MDP5_AD_START_CALC(uint32_t i0) REG_MDP5_AD_START_CALC() argument 1972 REG_MDP5_AD_STR_OUT(uint32_t i0) REG_MDP5_AD_STR_OUT() argument 1974 REG_MDP5_AD_BL_OUT(uint32_t i0) REG_MDP5_AD_BL_OUT() argument 1976 REG_MDP5_AD_CALC_DONE(uint32_t i0) REG_MDP5_AD_CALC_DONE() argument [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp4/
H A D	mdp4.xml.h	319 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument 321 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument 323 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument 337 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument 339 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument 341 REG_MDP4_OVLP_OPMODE(uint32_t i0) REG_MDP4_OVLP_OPMODE() argument 353 REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE() argument 355 REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_OP() argument 375 REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_FG_ALPHA() argument 377 REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_BG_ALPHA() argument 379 REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument 381 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument 383 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument 385 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument 397 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3() argument 399 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3_SEL() argument 402 REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW0() argument 404 REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW1() argument 406 REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH0() argument 408 REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH1() argument 410 REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) REG_MDP4_OVLP_CSC_CONFIG() argument 412 REG_MDP4_OVLP_CSC(uint32_t i0) REG_MDP4_OVLP_CSC() argument 415 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV() argument 417 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV_VAL() argument 419 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV() argument 421 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument 423 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV() argument 425 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV_VAL() argument 427 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV() argument 429 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument 431 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV() argument 433 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV_VAL() argument 437 REG_MDP4_LUTN(uint32_t i0) REG_MDP4_LUTN() argument 439 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT() argument 441 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT_VAL() argument 445 REG_MDP4_DMA_E_QUANT(uint32_t i0) REG_MDP4_DMA_E_QUANT() argument 456 REG_MDP4_DMA(enum mdp4_dma i0) REG_MDP4_DMA() argument 458 REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CONFIG() argument 487 REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_SIZE() argument 501 REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_BASE() argument 503 REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_STRIDE() argument 505 REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_DST_SIZE() argument 519 REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_SIZE() argument 533 REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BASE() argument 535 REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_POS() argument 549 REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument 559 REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument 561 REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_LOW() argument 563 REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_HIGH() argument 565 REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_FETCH_CONFIG() argument 567 REG_MDP4_DMA_CSC(enum mdp4_dma i0) REG_MDP4_DMA_CSC() argument 570 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV() argument 572 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV_VAL() argument 574 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV() argument 576 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV_VAL() argument 578 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV() argument 580 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV_VAL() argument 582 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV() argument 584 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV_VAL() argument 586 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV() argument 588 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV_VAL() argument 590 REG_MDP4_PIPE(enum mdp4_pipe i0) REG_MDP4_PIPE() argument 592 REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_SIZE() argument 606 REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_XY() argument 620 REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_SIZE() argument 634 REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_XY() argument 648 REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP0_BASE() argument 650 REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP1_BASE() argument 652 REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP2_BASE() argument 654 REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP3_BASE() argument 656 REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_A() argument 670 REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_B() argument 684 REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SSTILE_FRAME_SIZE() argument 698 REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_FORMAT() argument 759 REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_UNPACK() argument 785 REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) REG_MDP4_PIPE_OP_MODE() argument 810 REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEX_STEP() argument 812 REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEY_STEP() argument 814 REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) REG_MDP4_PIPE_FETCH_CONFIG() argument 816 REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) REG_MDP4_PIPE_SOLID_COLOR() argument 818 REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) REG_MDP4_PIPE_CSC() argument 821 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV() argument 823 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV_VAL() argument 825 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV() argument 827 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument 829 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV() argument 831 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV_VAL() argument 833 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV() argument 835 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument 837 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV() argument 839 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV_VAL() argument 938 REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL() argument 940 REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument 966 REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp4/
H A D	mdp4.xml.h	326 static inline uint32_t REG_MDP4_OVLP(uint32_t i0) { return 0x00000000 + __offset_OVLP(i0); } in REG_MDP4_OVLP() argument 328 static inline uint32_t REG_MDP4_OVLP_CFG(uint32_t i0) { return 0x00000004 + __offset_OVLP(i0); } in REG_MDP4_OVLP_CFG() argument 330 static inline uint32_t REG_MDP4_OVLP_SIZE(uint32_t i0) { return 0x00000008 + __offset_OVLP(i0); } in REG_MDP4_OVLP_SIZE() argument 344 static inline uint32_t REG_MDP4_OVLP_BASE(uint32_t i0) { return 0x0000000c + __offset_OVLP(i0); } in REG_MDP4_OVLP_BASE() argument 346 static inline uint32_t REG_MDP4_OVLP_STRIDE(uint32_t i0) { return 0x00000010 + __offset_OVLP(i0); } in REG_MDP4_OVLP_STRIDE() argument 348 REG_MDP4_OVLP_OPMODE(uint32_t i0) REG_MDP4_OVLP_OPMODE() argument 360 REG_MDP4_OVLP_STAGE(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE() argument 362 REG_MDP4_OVLP_STAGE_OP(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_OP() argument 382 REG_MDP4_OVLP_STAGE_FG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_FG_ALPHA() argument 384 REG_MDP4_OVLP_STAGE_BG_ALPHA(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_BG_ALPHA() argument 386 REG_MDP4_OVLP_STAGE_TRANSP_LOW0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW0() argument 388 REG_MDP4_OVLP_STAGE_TRANSP_LOW1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_LOW1() argument 390 REG_MDP4_OVLP_STAGE_TRANSP_HIGH0(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH0() argument 392 REG_MDP4_OVLP_STAGE_TRANSP_HIGH1(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_TRANSP_HIGH1() argument 404 REG_MDP4_OVLP_STAGE_CO3(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3() argument 406 REG_MDP4_OVLP_STAGE_CO3_SEL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_STAGE_CO3_SEL() argument 409 REG_MDP4_OVLP_TRANSP_LOW0(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW0() argument 411 REG_MDP4_OVLP_TRANSP_LOW1(uint32_t i0) REG_MDP4_OVLP_TRANSP_LOW1() argument 413 REG_MDP4_OVLP_TRANSP_HIGH0(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH0() argument 415 REG_MDP4_OVLP_TRANSP_HIGH1(uint32_t i0) REG_MDP4_OVLP_TRANSP_HIGH1() argument 417 REG_MDP4_OVLP_CSC_CONFIG(uint32_t i0) REG_MDP4_OVLP_CSC_CONFIG() argument 419 REG_MDP4_OVLP_CSC(uint32_t i0) REG_MDP4_OVLP_CSC() argument 422 REG_MDP4_OVLP_CSC_MV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV() argument 424 REG_MDP4_OVLP_CSC_MV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_MV_VAL() argument 426 REG_MDP4_OVLP_CSC_PRE_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV() argument 428 REG_MDP4_OVLP_CSC_PRE_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_BV_VAL() argument 430 REG_MDP4_OVLP_CSC_POST_BV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV() argument 432 REG_MDP4_OVLP_CSC_POST_BV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_BV_VAL() argument 434 REG_MDP4_OVLP_CSC_PRE_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV() argument 436 REG_MDP4_OVLP_CSC_PRE_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_PRE_LV_VAL() argument 438 REG_MDP4_OVLP_CSC_POST_LV(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV() argument 440 REG_MDP4_OVLP_CSC_POST_LV_VAL(uint32_t i0, uint32_t i1) REG_MDP4_OVLP_CSC_POST_LV_VAL() argument 444 REG_MDP4_LUTN(uint32_t i0) REG_MDP4_LUTN() argument 446 REG_MDP4_LUTN_LUT(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT() argument 448 REG_MDP4_LUTN_LUT_VAL(uint32_t i0, uint32_t i1) REG_MDP4_LUTN_LUT_VAL() argument 452 REG_MDP4_DMA_E_QUANT(uint32_t i0) REG_MDP4_DMA_E_QUANT() argument 463 REG_MDP4_DMA(enum mdp4_dma i0) REG_MDP4_DMA() argument 465 REG_MDP4_DMA_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CONFIG() argument 494 REG_MDP4_DMA_SRC_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_SIZE() argument 508 REG_MDP4_DMA_SRC_BASE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_BASE() argument 510 REG_MDP4_DMA_SRC_STRIDE(enum mdp4_dma i0) REG_MDP4_DMA_SRC_STRIDE() argument 512 REG_MDP4_DMA_DST_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_DST_SIZE() argument 526 REG_MDP4_DMA_CURSOR_SIZE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_SIZE() argument 540 REG_MDP4_DMA_CURSOR_BASE(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BASE() argument 542 REG_MDP4_DMA_CURSOR_POS(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_POS() argument 556 REG_MDP4_DMA_CURSOR_BLEND_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_CONFIG() argument 566 REG_MDP4_DMA_CURSOR_BLEND_PARAM(enum mdp4_dma i0) REG_MDP4_DMA_CURSOR_BLEND_PARAM() argument 568 REG_MDP4_DMA_BLEND_TRANS_LOW(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_LOW() argument 570 REG_MDP4_DMA_BLEND_TRANS_HIGH(enum mdp4_dma i0) REG_MDP4_DMA_BLEND_TRANS_HIGH() argument 572 REG_MDP4_DMA_FETCH_CONFIG(enum mdp4_dma i0) REG_MDP4_DMA_FETCH_CONFIG() argument 574 REG_MDP4_DMA_CSC(enum mdp4_dma i0) REG_MDP4_DMA_CSC() argument 577 REG_MDP4_DMA_CSC_MV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV() argument 579 REG_MDP4_DMA_CSC_MV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_MV_VAL() argument 581 REG_MDP4_DMA_CSC_PRE_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV() argument 583 REG_MDP4_DMA_CSC_PRE_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_BV_VAL() argument 585 REG_MDP4_DMA_CSC_POST_BV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV() argument 587 REG_MDP4_DMA_CSC_POST_BV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_BV_VAL() argument 589 REG_MDP4_DMA_CSC_PRE_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV() argument 591 REG_MDP4_DMA_CSC_PRE_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_PRE_LV_VAL() argument 593 REG_MDP4_DMA_CSC_POST_LV(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV() argument 595 REG_MDP4_DMA_CSC_POST_LV_VAL(enum mdp4_dma i0, uint32_t i1) REG_MDP4_DMA_CSC_POST_LV_VAL() argument 597 REG_MDP4_PIPE(enum mdp4_pipe i0) REG_MDP4_PIPE() argument 599 REG_MDP4_PIPE_SRC_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_SIZE() argument 613 REG_MDP4_PIPE_SRC_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_XY() argument 627 REG_MDP4_PIPE_DST_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_SIZE() argument 641 REG_MDP4_PIPE_DST_XY(enum mdp4_pipe i0) REG_MDP4_PIPE_DST_XY() argument 655 REG_MDP4_PIPE_SRCP0_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP0_BASE() argument 657 REG_MDP4_PIPE_SRCP1_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP1_BASE() argument 659 REG_MDP4_PIPE_SRCP2_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP2_BASE() argument 661 REG_MDP4_PIPE_SRCP3_BASE(enum mdp4_pipe i0) REG_MDP4_PIPE_SRCP3_BASE() argument 663 REG_MDP4_PIPE_SRC_STRIDE_A(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_A() argument 677 REG_MDP4_PIPE_SRC_STRIDE_B(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_STRIDE_B() argument 691 REG_MDP4_PIPE_SSTILE_FRAME_SIZE(enum mdp4_pipe i0) REG_MDP4_PIPE_SSTILE_FRAME_SIZE() argument 705 REG_MDP4_PIPE_SRC_FORMAT(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_FORMAT() argument 766 REG_MDP4_PIPE_SRC_UNPACK(enum mdp4_pipe i0) REG_MDP4_PIPE_SRC_UNPACK() argument 792 REG_MDP4_PIPE_OP_MODE(enum mdp4_pipe i0) REG_MDP4_PIPE_OP_MODE() argument 817 REG_MDP4_PIPE_PHASEX_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEX_STEP() argument 819 REG_MDP4_PIPE_PHASEY_STEP(enum mdp4_pipe i0) REG_MDP4_PIPE_PHASEY_STEP() argument 821 REG_MDP4_PIPE_FETCH_CONFIG(enum mdp4_pipe i0) REG_MDP4_PIPE_FETCH_CONFIG() argument 823 REG_MDP4_PIPE_SOLID_COLOR(enum mdp4_pipe i0) REG_MDP4_PIPE_SOLID_COLOR() argument 825 REG_MDP4_PIPE_CSC(enum mdp4_pipe i0) REG_MDP4_PIPE_CSC() argument 828 REG_MDP4_PIPE_CSC_MV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV() argument 830 REG_MDP4_PIPE_CSC_MV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_MV_VAL() argument 832 REG_MDP4_PIPE_CSC_PRE_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV() argument 834 REG_MDP4_PIPE_CSC_PRE_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_BV_VAL() argument 836 REG_MDP4_PIPE_CSC_POST_BV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV() argument 838 REG_MDP4_PIPE_CSC_POST_BV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_BV_VAL() argument 840 REG_MDP4_PIPE_CSC_PRE_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV() argument 842 REG_MDP4_PIPE_CSC_PRE_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_PRE_LV_VAL() argument 844 REG_MDP4_PIPE_CSC_POST_LV(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV() argument 846 REG_MDP4_PIPE_CSC_POST_LV_VAL(enum mdp4_pipe i0, uint32_t i1) REG_MDP4_PIPE_CSC_POST_LV_VAL() argument 945 REG_MDP4_LCDC_LVDS_MUX_CTL(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL() argument 947 REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_3_TO_0() argument 973 REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4(uint32_t i0) REG_MDP4_LCDC_LVDS_MUX_CTL_6_TO_4() argument [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/dsi/
H A D	dsi_phy_10nm.xml.h	126 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN() argument 128 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG0() argument 130 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG1() argument 132 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG2() argument 134 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3() argument 136 REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_10nm_PHY_LN_TEST_DATAPATH() argument 138 REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) REG_DSI_10nm_PHY_LN_PIN_SWAP() argument 140 REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL() argument 142 REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL() argument 144 REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL() argument 146 REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL() argument 148 REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPRX_CTRL() argument 150 REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_TX_DCTRL() argument [all...]
H A D	dsi_phy_14nm.xml.h	117 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN() argument 119 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG0() argument 127 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG1() argument 130 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG2() argument 132 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3() argument 134 REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_DATAPATH() argument 136 REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_STR() argument 138 REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_4() argument 146 REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_5() argument 154 REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_6() argument 162 REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_7() argument 170 REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_8() argument 178 REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_9() argument 192 REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_10() argument 200 REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_11() argument 208 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0() argument 210 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1() argument 212 REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) REG_DSI_14nm_PHY_LN_VREG_CNTRL() argument [all...]
H A D	dsi_phy_20nm.xml.h	56 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN() argument 58 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3() argument 66 REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_4() argument 68 REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_DATAPATH() argument 70 REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_20nm_PHY_LN_DEBUG_SEL() argument 72 REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_0() argument 74 REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_1() argument [all...]
H A D	dsi_phy_28nm_8960.xml.h	56 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument 58 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument 66 REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument 68 REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument [all...]
H A D	dsi_phy_28nm.xml.h	56 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN() argument 58 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0() argument 60 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1() argument 62 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2() argument 64 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3() argument 66 REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_4() argument 68 REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument 70 REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument 72 REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_0() argument 74 REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_1() argument [all...]
H A D	mmss_cc.xml.h	71 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK() argument 73 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_CC() argument 90 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_MD() argument 104 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_NS() argument
/kernel/linux/linux-5.10/arch/sparc/lib/
H A D	divdi3.S	14 cmp %i0,0 21 sub %g0,%i0,%o0 23 mov %o4,%i0 42 cmp %o4,%i0 46 subcc %i0,%o4,%g0 49 sub %i0,%o4,%i0 ! this kills msb of n 50 addx %i0,%i0,%i0 ! s [all...]
H A D	udivdi3.S	17 cmp %o3,%i0 22 subcc %i0,%o3,%g0 25 sub %i0,%o3,%i0 ! this kills msb of n 26 addx %i0,%i0,%i0 ! so this cannot give carry 29 subcc %i0,%o3,%g0 33 sub %i0,%o3,%i0 ! thi [all...]
H A D	NGpage.S	33 stxa %o2, [%i0 + 0x00] %asi 34 stxa %o3, [%i0 + 0x08] %asi 35 stxa %o4, [%i0 + 0x10] %asi 36 stxa %o5, [%i0 + 0x18] %asi 37 stxa %l2, [%i0 + 0x20] %asi 38 stxa %l3, [%i0 + 0x28] %asi 39 stxa %l4, [%i0 + 0x30] %asi 40 stxa %l5, [%i0 + 0x38] %asi 45 stxa %o2, [%i0 + 0x40] %asi 46 stxa %o3, [%i0 [all...]
/kernel/linux/linux-6.6/arch/sparc/lib/
H A D	divdi3.S	14 cmp %i0,0 21 sub %g0,%i0,%o0 23 mov %o4,%i0 42 cmp %o4,%i0 46 subcc %i0,%o4,%g0 49 sub %i0,%o4,%i0 ! this kills msb of n 50 addx %i0,%i0,%i0 ! s [all...]
H A D	udivdi3.S	17 cmp %o3,%i0 22 subcc %i0,%o3,%g0 25 sub %i0,%o3,%i0 ! this kills msb of n 26 addx %i0,%i0,%i0 ! so this cannot give carry 29 subcc %i0,%o3,%g0 33 sub %i0,%o3,%i0 ! thi [all...]
H A D	NGpage.S	33 stxa %o2, [%i0 + 0x00] %asi 34 stxa %o3, [%i0 + 0x08] %asi 35 stxa %o4, [%i0 + 0x10] %asi 36 stxa %o5, [%i0 + 0x18] %asi 37 stxa %l2, [%i0 + 0x20] %asi 38 stxa %l3, [%i0 + 0x28] %asi 39 stxa %l4, [%i0 + 0x30] %asi 40 stxa %l5, [%i0 + 0x38] %asi 45 stxa %o2, [%i0 + 0x40] %asi 46 stxa %o3, [%i0 [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/etnaviv/
H A D	state.xml.h	73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) 192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) 198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/etnaviv/
H A D	state.xml.h	73 #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0) (0x00000600 + 0x4*(i0)) 192 #define VIVS_FE_VERTEX_STREAMS(i0) (0x00000000 + 0x4*(i0)) 196 #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0) (0x00000680 + 0x4*(i0)) 198 #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0) (0x000006a0 + 0x4*(i0)) 200 #define VIVS_FE_GENERIC_ATTRIB(i0) (0x00000000 + 0x4*(i0)) [all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/dsi/
H A D	dsi.xml.h	415 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK() argument 417 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA() argument 731 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN() argument 733 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0() argument 735 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1() argument 737 REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_CFG_2() argument 739 REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH() argument 741 REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_0() argument 743 REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_8960_PHY_LN_TEST_STR_1() argument 960 REG_DSI_28nm_PHY_LN(uint32_t i0) REG_DSI_28nm_PHY_LN() argument 962 REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_0() argument 964 REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_1() argument 966 REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_2() argument 968 REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_3() argument 970 REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_28nm_PHY_LN_CFG_4() argument 972 REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_DATAPATH() argument 974 REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_28nm_PHY_LN_DEBUG_SEL() argument 976 REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_0() argument 978 REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_28nm_PHY_LN_TEST_STR_1() argument 1287 REG_DSI_20nm_PHY_LN(uint32_t i0) REG_DSI_20nm_PHY_LN() argument 1289 REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_0() argument 1291 REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_1() argument 1293 REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_2() argument 1295 REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_3() argument 1297 REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) REG_DSI_20nm_PHY_LN_CFG_4() argument 1299 REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_DATAPATH() argument 1301 REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) REG_DSI_20nm_PHY_LN_DEBUG_SEL() argument 1303 REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_0() argument 1305 REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) REG_DSI_20nm_PHY_LN_TEST_STR_1() argument 1528 REG_DSI_14nm_PHY_LN(uint32_t i0) REG_DSI_14nm_PHY_LN() argument 1530 REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) REG_DSI_14nm_PHY_LN_CFG0() argument 1538 REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) REG_DSI_14nm_PHY_LN_CFG1() argument 1541 REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) REG_DSI_14nm_PHY_LN_CFG2() argument 1543 REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) REG_DSI_14nm_PHY_LN_CFG3() argument 1545 REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_DATAPATH() argument 1547 REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) REG_DSI_14nm_PHY_LN_TEST_STR() argument 1549 REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_4() argument 1557 REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_5() argument 1565 REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_6() argument 1573 REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_7() argument 1581 REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_8() argument 1589 REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_9() argument 1603 REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_10() argument 1611 REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) REG_DSI_14nm_PHY_LN_TIMING_CTRL_11() argument 1619 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0() argument 1621 REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1() argument 1623 REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) REG_DSI_14nm_PHY_LN_VREG_CNTRL() argument 1789 REG_DSI_10nm_PHY_LN(uint32_t i0) REG_DSI_10nm_PHY_LN() argument 1791 REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) REG_DSI_10nm_PHY_LN_CFG0() argument 1793 REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) REG_DSI_10nm_PHY_LN_CFG1() argument 1795 REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) REG_DSI_10nm_PHY_LN_CFG2() argument 1797 REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) REG_DSI_10nm_PHY_LN_CFG3() argument 1799 REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_10nm_PHY_LN_TEST_DATAPATH() argument 1801 REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) REG_DSI_10nm_PHY_LN_PIN_SWAP() argument 1803 REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL() argument 1805 REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL() argument 1807 REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL() argument 1809 REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL() argument 1811 REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_LPRX_CTRL() argument 1813 REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) REG_DSI_10nm_PHY_LN_TX_DCTRL() argument 1991 REG_DSI_7nm_PHY_LN(uint32_t i0) REG_DSI_7nm_PHY_LN() argument 1993 REG_DSI_7nm_PHY_LN_CFG0(uint32_t i0) REG_DSI_7nm_PHY_LN_CFG0() argument 1995 REG_DSI_7nm_PHY_LN_CFG1(uint32_t i0) REG_DSI_7nm_PHY_LN_CFG1() argument 1997 REG_DSI_7nm_PHY_LN_CFG2(uint32_t i0) REG_DSI_7nm_PHY_LN_CFG2() argument 1999 REG_DSI_7nm_PHY_LN_TEST_DATAPATH(uint32_t i0) REG_DSI_7nm_PHY_LN_TEST_DATAPATH() argument 2001 REG_DSI_7nm_PHY_LN_PIN_SWAP(uint32_t i0) REG_DSI_7nm_PHY_LN_PIN_SWAP() argument 2003 REG_DSI_7nm_PHY_LN_LPRX_CTRL(uint32_t i0) REG_DSI_7nm_PHY_LN_LPRX_CTRL() argument 2005 REG_DSI_7nm_PHY_LN_TX_DCTRL(uint32_t i0) REG_DSI_7nm_PHY_LN_TX_DCTRL() argument [all...]
H A D	mmss_cc.xml.h	64 static inline uint32_t REG_MMSS_CC_CLK(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK() argument 66 static inline uint32_t REG_MMSS_CC_CLK_CC(enum mmss_cc_clk i0) { return 0x00000000 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_CC() argument 83 static inline uint32_t REG_MMSS_CC_CLK_MD(enum mmss_cc_clk i0) { return 0x00000004 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_MD() argument 97 static inline uint32_t REG_MMSS_CC_CLK_NS(enum mmss_cc_clk i0) { return 0x00000008 + __offset_CLK(i0); } in REG_MMSS_CC_CLK_NS() argument
/kernel/linux/linux-5.10/arch/arm64/crypto/
H A D	aes-ce.S	57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4 58 aes\de \i0\().16b, \k\().16b 59 aes\mc \i0\().16b, \i0\().16b 77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4 79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4 81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4 86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4 87 aes\de \i0\().16b, \k\().16b 98 eor \i0\() [all...]
/kernel/linux/linux-6.6/arch/arm64/crypto/
H A D	aes-ce.S	57 .macro do_enc_Nx, de, mc, k, i0, i1, i2, i3, i4 58 aes\de \i0\().16b, \k\().16b 59 aes\mc \i0\().16b, \i0\().16b 77 .macro round_Nx, enc, k, i0, i1, i2, i3, i4 79 do_enc_Nx e, mc, \k, \i0, \i1, \i2, \i3, \i4 81 do_enc_Nx d, imc, \k, \i0, \i1, \i2, \i3, \i4 86 .macro fin_round_Nx, de, k, k2, i0, i1, i2, i3, i4 87 aes\de \i0\().16b, \k\().16b 98 eor \i0\() [all...]
/kernel/linux/linux-5.10/fs/jffs2/
H A D	compr_rubin.c	105 long i0, i1; in encode() local 119 i0 = A * rs->p / (A + B); in encode() 120 if (i0 <= 0) in encode() 121 i0 = 1; in encode() 123 if (i0 >= rs->p) in encode() 124 i0 = rs->p - 1; in encode() 126 i1 = rs->p - i0; in encode() 129 rs->p = i0; in encode() 132 rs->q += i0; in encode() 203 long i0, threshol in decode() local [all...]
/kernel/linux/linux-6.6/fs/jffs2/
H A D	compr_rubin.c	105 long i0, i1; in encode() local 119 i0 = A * rs->p / (A + B); in encode() 120 if (i0 <= 0) in encode() 121 i0 = 1; in encode() 123 if (i0 >= rs->p) in encode() 124 i0 = rs->p - 1; in encode() 126 i1 = rs->p - i0; in encode() 129 rs->p = i0; in encode() 132 rs->q += i0; in encode() 203 long i0, threshol in decode() local [all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/
H A D	a6xx.xml.h	1173 static inline uint32_t REG_A6XX_CP_SCRATCH(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH() argument 1175 static inline uint32_t REG_A6XX_CP_SCRATCH_REG(uint32_t i0) { return 0x00000883 + 0x1*i0; } in REG_A6XX_CP_SCRATCH_REG() argument 1177 static inline uint32_t REG_A6XX_CP_PROTECT(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT() argument 1179 static inline uint32_t REG_A6XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000850 + 0x1*i0; } in REG_A6XX_CP_PROTECT_REG() argument 1206 static inline uint32_t REG_A6XX_CP_PERFCTR_CP_SEL(uint32_t i0) { return 0x000008d0 + 0x1*i0; } in REG_A6XX_CP_PERFCTR_CP_SEL() argument 1208 REG_A7XX_CP_BV_PERFCTR_CP_SEL(uint32_t i0) REG_A7XX_CP_BV_PERFCTR_CP_SEL() argument 1517 REG_A6XX_RBBM_PERFCTR_CP(uint32_t i0) REG_A6XX_RBBM_PERFCTR_CP() argument 1519 REG_A6XX_RBBM_PERFCTR_RBBM(uint32_t i0) REG_A6XX_RBBM_PERFCTR_RBBM() argument 1521 REG_A6XX_RBBM_PERFCTR_PC(uint32_t i0) REG_A6XX_RBBM_PERFCTR_PC() argument 1523 REG_A6XX_RBBM_PERFCTR_VFD(uint32_t i0) REG_A6XX_RBBM_PERFCTR_VFD() argument 1525 REG_A6XX_RBBM_PERFCTR_HLSQ(uint32_t i0) REG_A6XX_RBBM_PERFCTR_HLSQ() argument 1527 REG_A6XX_RBBM_PERFCTR_VPC(uint32_t i0) REG_A6XX_RBBM_PERFCTR_VPC() argument 1529 REG_A6XX_RBBM_PERFCTR_CCU(uint32_t i0) REG_A6XX_RBBM_PERFCTR_CCU() argument 1531 REG_A6XX_RBBM_PERFCTR_TSE(uint32_t i0) REG_A6XX_RBBM_PERFCTR_TSE() argument 1533 REG_A6XX_RBBM_PERFCTR_RAS(uint32_t i0) REG_A6XX_RBBM_PERFCTR_RAS() argument 1535 REG_A6XX_RBBM_PERFCTR_UCHE(uint32_t i0) REG_A6XX_RBBM_PERFCTR_UCHE() argument 1537 REG_A6XX_RBBM_PERFCTR_TP(uint32_t i0) REG_A6XX_RBBM_PERFCTR_TP() argument 1539 REG_A6XX_RBBM_PERFCTR_SP(uint32_t i0) REG_A6XX_RBBM_PERFCTR_SP() argument 1541 REG_A6XX_RBBM_PERFCTR_RB(uint32_t i0) REG_A6XX_RBBM_PERFCTR_RB() argument 1543 REG_A6XX_RBBM_PERFCTR_VSC(uint32_t i0) REG_A6XX_RBBM_PERFCTR_VSC() argument 1545 REG_A6XX_RBBM_PERFCTR_LRZ(uint32_t i0) REG_A6XX_RBBM_PERFCTR_LRZ() argument 1547 REG_A6XX_RBBM_PERFCTR_CMP(uint32_t i0) REG_A6XX_RBBM_PERFCTR_CMP() argument 1549 REG_A7XX_RBBM_PERFCTR_CP(uint32_t i0) REG_A7XX_RBBM_PERFCTR_CP() argument 1551 REG_A7XX_RBBM_PERFCTR_RBBM(uint32_t i0) REG_A7XX_RBBM_PERFCTR_RBBM() argument 1553 REG_A7XX_RBBM_PERFCTR_PC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_PC() argument 1555 REG_A7XX_RBBM_PERFCTR_VFD(uint32_t i0) REG_A7XX_RBBM_PERFCTR_VFD() argument 1557 REG_A7XX_RBBM_PERFCTR_HLSQ(uint32_t i0) REG_A7XX_RBBM_PERFCTR_HLSQ() argument 1559 REG_A7XX_RBBM_PERFCTR_VPC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_VPC() argument 1561 REG_A7XX_RBBM_PERFCTR_CCU(uint32_t i0) REG_A7XX_RBBM_PERFCTR_CCU() argument 1563 REG_A7XX_RBBM_PERFCTR_TSE(uint32_t i0) REG_A7XX_RBBM_PERFCTR_TSE() argument 1565 REG_A7XX_RBBM_PERFCTR_RAS(uint32_t i0) REG_A7XX_RBBM_PERFCTR_RAS() argument 1567 REG_A7XX_RBBM_PERFCTR_UCHE(uint32_t i0) REG_A7XX_RBBM_PERFCTR_UCHE() argument 1569 REG_A7XX_RBBM_PERFCTR_TP(uint32_t i0) REG_A7XX_RBBM_PERFCTR_TP() argument 1571 REG_A7XX_RBBM_PERFCTR_SP(uint32_t i0) REG_A7XX_RBBM_PERFCTR_SP() argument 1573 REG_A7XX_RBBM_PERFCTR_RB(uint32_t i0) REG_A7XX_RBBM_PERFCTR_RB() argument 1575 REG_A7XX_RBBM_PERFCTR_VSC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_VSC() argument 1577 REG_A7XX_RBBM_PERFCTR_LRZ(uint32_t i0) REG_A7XX_RBBM_PERFCTR_LRZ() argument 1579 REG_A7XX_RBBM_PERFCTR_CMP(uint32_t i0) REG_A7XX_RBBM_PERFCTR_CMP() argument 1581 REG_A7XX_RBBM_PERFCTR_UFC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_UFC() argument 1583 REG_A7XX_RBBM_PERFCTR2_HLSQ(uint32_t i0) REG_A7XX_RBBM_PERFCTR2_HLSQ() argument 1585 REG_A7XX_RBBM_PERFCTR2_CP(uint32_t i0) REG_A7XX_RBBM_PERFCTR2_CP() argument 1587 REG_A7XX_RBBM_PERFCTR2_SP(uint32_t i0) REG_A7XX_RBBM_PERFCTR2_SP() argument 1589 REG_A7XX_RBBM_PERFCTR2_TP(uint32_t i0) REG_A7XX_RBBM_PERFCTR2_TP() argument 1591 REG_A7XX_RBBM_PERFCTR2_UFC(uint32_t i0) REG_A7XX_RBBM_PERFCTR2_UFC() argument 1593 REG_A7XX_RBBM_PERFCTR_BV_PC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_PC() argument 1595 REG_A7XX_RBBM_PERFCTR_BV_VFD(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_VFD() argument 1597 REG_A7XX_RBBM_PERFCTR_BV_VPC(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_VPC() argument 1599 REG_A7XX_RBBM_PERFCTR_BV_TSE(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_TSE() argument 1601 REG_A7XX_RBBM_PERFCTR_BV_RAS(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_RAS() argument 1603 REG_A7XX_RBBM_PERFCTR_BV_LRZ(uint32_t i0) REG_A7XX_RBBM_PERFCTR_BV_LRZ() argument 1619 REG_A6XX_RBBM_PERFCTR_RBBM_SEL(uint32_t i0) REG_A6XX_RBBM_PERFCTR_RBBM_SEL() argument 2112 REG_A6XX_VSC_PERFCTR_VSC_SEL(uint32_t i0) REG_A6XX_VSC_PERFCTR_VSC_SEL() argument 2144 REG_A6XX_UCHE_PERFCTR_UCHE_SEL(uint32_t i0) REG_A6XX_UCHE_PERFCTR_UCHE_SEL() argument 2311 REG_A6XX_VSC_PIPE_CONFIG(uint32_t i0) REG_A6XX_VSC_PIPE_CONFIG() argument 2313 REG_A6XX_VSC_PIPE_CONFIG_REG(uint32_t i0) REG_A6XX_VSC_PIPE_CONFIG_REG() argument 2351 REG_A6XX_VSC_STATE(uint32_t i0) REG_A6XX_VSC_STATE() argument 2353 REG_A6XX_VSC_STATE_REG(uint32_t i0) REG_A6XX_VSC_STATE_REG() argument 2355 REG_A6XX_VSC_PRIM_STRM_SIZE(uint32_t i0) REG_A6XX_VSC_PRIM_STRM_SIZE() argument 2357 REG_A6XX_VSC_PRIM_STRM_SIZE_REG(uint32_t i0) REG_A6XX_VSC_PRIM_STRM_SIZE_REG() argument 2359 REG_A6XX_VSC_DRAW_STRM_SIZE(uint32_t i0) REG_A6XX_VSC_DRAW_STRM_SIZE() argument 2361 REG_A6XX_VSC_DRAW_STRM_SIZE_REG(uint32_t i0) REG_A6XX_VSC_DRAW_STRM_SIZE_REG() argument 2447 REG_A6XX_GRAS_CL_VPORT(uint32_t i0) REG_A6XX_GRAS_CL_VPORT() argument 2449 REG_A6XX_GRAS_CL_VPORT_XOFFSET(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_XOFFSET() argument 2457 REG_A6XX_GRAS_CL_VPORT_XSCALE(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_XSCALE() argument 2465 REG_A6XX_GRAS_CL_VPORT_YOFFSET(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_YOFFSET() argument 2473 REG_A6XX_GRAS_CL_VPORT_YSCALE(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_YSCALE() argument 2481 REG_A6XX_GRAS_CL_VPORT_ZOFFSET(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_ZOFFSET() argument 2489 REG_A6XX_GRAS_CL_VPORT_ZSCALE(uint32_t i0) REG_A6XX_GRAS_CL_VPORT_ZSCALE() argument 2497 REG_A6XX_GRAS_CL_Z_CLAMP(uint32_t i0) REG_A6XX_GRAS_CL_Z_CLAMP() argument 2499 REG_A6XX_GRAS_CL_Z_CLAMP_MIN(uint32_t i0) REG_A6XX_GRAS_CL_Z_CLAMP_MIN() argument 2507 REG_A6XX_GRAS_CL_Z_CLAMP_MAX(uint32_t i0) REG_A6XX_GRAS_CL_Z_CLAMP_MAX() argument 2867 REG_A6XX_GRAS_SC_SCREEN_SCISSOR(uint32_t i0) REG_A6XX_GRAS_SC_SCREEN_SCISSOR() argument 2869 REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL(uint32_t i0) REG_A6XX_GRAS_SC_SCREEN_SCISSOR_TL() argument 2883 REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR(uint32_t i0) REG_A6XX_GRAS_SC_SCREEN_SCISSOR_BR() argument 2897 REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR(uint32_t i0) REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR() argument 2899 REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL(uint32_t i0) REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_TL() argument 2913 REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR(uint32_t i0) REG_A6XX_GRAS_SC_VIEWPORT_SCISSOR_BR() argument 3169 REG_A6XX_GRAS_PERFCTR_TSE_SEL(uint32_t i0) REG_A6XX_GRAS_PERFCTR_TSE_SEL() argument 3171 REG_A6XX_GRAS_PERFCTR_RAS_SEL(uint32_t i0) REG_A6XX_GRAS_PERFCTR_RAS_SEL() argument 3173 REG_A6XX_GRAS_PERFCTR_LRZ_SEL(uint32_t i0) REG_A6XX_GRAS_PERFCTR_LRZ_SEL() argument 3551 REG_A6XX_RB_MRT(uint32_t i0) REG_A6XX_RB_MRT() argument 3553 REG_A6XX_RB_MRT_CONTROL(uint32_t i0) REG_A6XX_RB_MRT_CONTROL() argument 3570 REG_A6XX_RB_MRT_BLEND_CONTROL(uint32_t i0) REG_A6XX_RB_MRT_BLEND_CONTROL() argument 3608 REG_A6XX_RB_MRT_BUF_INFO(uint32_t i0) REG_A6XX_RB_MRT_BUF_INFO() argument 3634 REG_A6XX_RB_MRT_PITCH(uint32_t i0) REG_A6XX_RB_MRT_PITCH() argument 3642 REG_A6XX_RB_MRT_ARRAY_PITCH(uint32_t i0) REG_A6XX_RB_MRT_ARRAY_PITCH() argument 3650 REG_A6XX_RB_MRT_BASE(uint32_t i0) REG_A6XX_RB_MRT_BASE() argument 3658 REG_A6XX_RB_MRT_BASE_GMEM(uint32_t i0) REG_A6XX_RB_MRT_BASE_GMEM() argument 4228 REG_A6XX_RB_MRT_FLAG_BUFFER(uint32_t i0) REG_A6XX_RB_MRT_FLAG_BUFFER() argument 4230 REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR(uint32_t i0) REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR() argument 4238 REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH(uint32_t i0) REG_A6XX_RB_MRT_FLAG_BUFFER_PITCH() argument 4498 REG_A6XX_RB_PERFCTR_RB_SEL(uint32_t i0) REG_A6XX_RB_PERFCTR_RB_SEL() argument 4500 REG_A6XX_RB_PERFCTR_CCU_SEL(uint32_t i0) REG_A6XX_RB_PERFCTR_CCU_SEL() argument 4504 REG_A6XX_RB_PERFCTR_CMP_SEL(uint32_t i0) REG_A6XX_RB_PERFCTR_CMP_SEL() argument 4506 REG_A7XX_RB_PERFCTR_UFC_SEL(uint32_t i0) REG_A7XX_RB_PERFCTR_UFC_SEL() argument 4644 REG_A6XX_VPC_VARYING_INTERP(uint32_t i0) REG_A6XX_VPC_VARYING_INTERP() argument 4646 REG_A6XX_VPC_VARYING_INTERP_MODE(uint32_t i0) REG_A6XX_VPC_VARYING_INTERP_MODE() argument 4648 REG_A6XX_VPC_VARYING_PS_REPL(uint32_t i0) REG_A6XX_VPC_VARYING_PS_REPL() argument 4650 REG_A6XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) REG_A6XX_VPC_VARYING_PS_REPL_MODE() argument 4656 REG_A6XX_VPC_VAR(uint32_t i0) REG_A6XX_VPC_VAR() argument 4658 REG_A6XX_VPC_VAR_DISABLE(uint32_t i0) REG_A6XX_VPC_VAR_DISABLE() argument 4705 REG_A6XX_VPC_SO(uint32_t i0) REG_A6XX_VPC_SO() argument 4707 REG_A6XX_VPC_SO_BUFFER_BASE(uint32_t i0) REG_A6XX_VPC_SO_BUFFER_BASE() argument 4715 REG_A6XX_VPC_SO_BUFFER_SIZE(uint32_t i0) REG_A6XX_VPC_SO_BUFFER_SIZE() argument 4723 REG_A6XX_VPC_SO_BUFFER_STRIDE(uint32_t i0) REG_A6XX_VPC_SO_BUFFER_STRIDE() argument 4731 REG_A6XX_VPC_SO_BUFFER_OFFSET(uint32_t i0) REG_A6XX_VPC_SO_BUFFER_OFFSET() argument 4739 REG_A6XX_VPC_SO_FLUSH_BASE(uint32_t i0) REG_A6XX_VPC_SO_FLUSH_BASE() argument 4894 REG_A6XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) REG_A6XX_VPC_PERFCTR_VPC_SEL() argument 4896 REG_A7XX_VPC_PERFCTR_VPC_SEL(uint32_t i0) REG_A7XX_VPC_PERFCTR_VPC_SEL() argument 5230 REG_A6XX_PC_PERFCTR_PC_SEL(uint32_t i0) REG_A6XX_PC_PERFCTR_PC_SEL() argument 5232 REG_A7XX_PC_PERFCTR_PC_SEL(uint32_t i0) REG_A7XX_PC_PERFCTR_PC_SEL() argument 5367 REG_A6XX_VFD_FETCH(uint32_t i0) REG_A6XX_VFD_FETCH() argument 5369 REG_A6XX_VFD_FETCH_BASE(uint32_t i0) REG_A6XX_VFD_FETCH_BASE() argument 5377 REG_A6XX_VFD_FETCH_SIZE(uint32_t i0) REG_A6XX_VFD_FETCH_SIZE() argument 5379 REG_A6XX_VFD_FETCH_STRIDE(uint32_t i0) REG_A6XX_VFD_FETCH_STRIDE() argument 5381 REG_A6XX_VFD_DECODE(uint32_t i0) REG_A6XX_VFD_DECODE() argument 5383 REG_A6XX_VFD_DECODE_INSTR(uint32_t i0) REG_A6XX_VFD_DECODE_INSTR() argument 5412 REG_A6XX_VFD_DECODE_STEP_RATE(uint32_t i0) REG_A6XX_VFD_DECODE_STEP_RATE() argument 5414 REG_A6XX_VFD_DEST_CNTL(uint32_t i0) REG_A6XX_VFD_DEST_CNTL() argument 5416 REG_A6XX_VFD_DEST_CNTL_INSTR(uint32_t i0) REG_A6XX_VFD_DEST_CNTL_INSTR() argument 5434 REG_A6XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) REG_A6XX_VFD_PERFCTR_VFD_SEL() argument 5436 REG_A7XX_VFD_PERFCTR_VFD_SEL(uint32_t i0) REG_A7XX_VFD_PERFCTR_VFD_SEL() argument 5483 REG_A6XX_SP_VS_OUT(uint32_t i0) REG_A6XX_SP_VS_OUT() argument 5485 REG_A6XX_SP_VS_OUT_REG(uint32_t i0) REG_A6XX_SP_VS_OUT_REG() argument 5511 REG_A6XX_SP_VS_VPC_DST(uint32_t i0) REG_A6XX_SP_VS_VPC_DST() argument 5513 REG_A6XX_SP_VS_VPC_DST_REG(uint32_t i0) REG_A6XX_SP_VS_VPC_DST_REG() argument 5771 REG_A6XX_SP_DS_OUT(uint32_t i0) REG_A6XX_SP_DS_OUT() argument 5773 REG_A6XX_SP_DS_OUT_REG(uint32_t i0) REG_A6XX_SP_DS_OUT_REG() argument 5799 REG_A6XX_SP_DS_VPC_DST(uint32_t i0) REG_A6XX_SP_DS_VPC_DST() argument 5801 REG_A6XX_SP_DS_VPC_DST_REG(uint32_t i0) REG_A6XX_SP_DS_VPC_DST_REG() argument 5951 REG_A6XX_SP_GS_OUT(uint32_t i0) REG_A6XX_SP_GS_OUT() argument 5953 REG_A6XX_SP_GS_OUT_REG(uint32_t i0) REG_A6XX_SP_GS_OUT_REG() argument 5979 REG_A6XX_SP_GS_VPC_DST(uint32_t i0) REG_A6XX_SP_GS_VPC_DST() argument 5981 REG_A6XX_SP_GS_VPC_DST_REG(uint32_t i0) REG_A6XX_SP_GS_VPC_DST_REG() argument 6334 REG_A6XX_SP_FS_OUTPUT(uint32_t i0) REG_A6XX_SP_FS_OUTPUT() argument 6336 REG_A6XX_SP_FS_OUTPUT_REG(uint32_t i0) REG_A6XX_SP_FS_OUTPUT_REG() argument 6345 REG_A6XX_SP_FS_MRT(uint32_t i0) REG_A6XX_SP_FS_MRT() argument 6347 REG_A6XX_SP_FS_MRT_REG(uint32_t i0) REG_A6XX_SP_FS_MRT_REG() argument 6375 REG_A6XX_SP_FS_PREFETCH(uint32_t i0) REG_A6XX_SP_FS_PREFETCH() argument 6377 REG_A6XX_SP_FS_PREFETCH_CMD(uint32_t i0) REG_A6XX_SP_FS_PREFETCH_CMD() argument 6418 REG_A6XX_SP_FS_BINDLESS_PREFETCH(uint32_t i0) REG_A6XX_SP_FS_BINDLESS_PREFETCH() argument 6420 REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD(uint32_t i0) REG_A6XX_SP_FS_BINDLESS_PREFETCH_CMD() argument 6647 REG_A6XX_SP_CS_BINDLESS_BASE(uint32_t i0) REG_A6XX_SP_CS_BINDLESS_BASE() argument 6649 REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) REG_A6XX_SP_CS_BINDLESS_BASE_DESCRIPTOR() argument 6710 REG_A6XX_SP_BINDLESS_BASE(uint32_t i0) REG_A6XX_SP_BINDLESS_BASE() argument 6712 REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) REG_A6XX_SP_BINDLESS_BASE_DESCRIPTOR() argument 6773 REG_A6XX_SP_PERFCTR_SP_SEL(uint32_t i0) REG_A6XX_SP_PERFCTR_SP_SEL() argument 6775 REG_A7XX_SP_PERFCTR_HLSQ_SEL(uint32_t i0) REG_A7XX_SP_PERFCTR_HLSQ_SEL() argument 6779 REG_A7XX_SP_PERFCTR_SP_SEL(uint32_t i0) REG_A7XX_SP_PERFCTR_SP_SEL() argument 7142 REG_A6XX_TPL1_PERFCTR_TP_SEL(uint32_t i0) REG_A6XX_TPL1_PERFCTR_TP_SEL() argument 7540 REG_A6XX_HLSQ_CS_BINDLESS_BASE(uint32_t i0) REG_A6XX_HLSQ_CS_BINDLESS_BASE() argument 7542 REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) REG_A6XX_HLSQ_CS_BINDLESS_BASE_DESCRIPTOR() argument 7632 REG_A6XX_HLSQ_BINDLESS_BASE(uint32_t i0) REG_A6XX_HLSQ_BINDLESS_BASE() argument 7634 REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR(uint32_t i0) REG_A6XX_HLSQ_BINDLESS_BASE_DESCRIPTOR() argument 7672 REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL(uint32_t i0) REG_A6XX_HLSQ_PERFCTR_HLSQ_SEL() argument [all...]

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Indexes created Thu Nov 07 10:32:03 CST 2024