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Searched refs:flush_mask (Results 1 - 23 of 23) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.c37 /* pending flush_mask bits */
38 u32 flush_mask; member
471 u32 flush_mask) in fix_sw_flush()
476 (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) in fix_sw_flush()
485 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, in fix_for_single_flush() argument
491 DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); in fix_for_single_flush()
493 ctl_mgr->single_flush_pending_mask |= (*flush_mask); in fix_for_single_flush()
494 *flush_mask = 0; in fix_for_single_flush()
498 *flush_mask = ctl_mgr->single_flush_pending_mask; in fix_for_single_flush()
504 DBG("Single FLUSH mask %x,ID %d", *flush_mask, in fix_for_single_flush()
470 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask) fix_sw_flush() argument
526 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask, bool start) mdp5_ctl_commit() argument
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H A Dmdp5_crtc.c87 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) in crtc_flush() argument
96 DBG("%s: flush=%08x", crtc->name, flush_mask); in crtc_flush()
98 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
111 uint32_t flush_mask = 0; in crtc_flush_all() local
120 flush_mask |= mdp5_plane_get_flush(plane); in crtc_flush_all()
124 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); in crtc_flush_all()
128 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); in crtc_flush_all()
130 return crtc_flush(crtc, flush_mask); in crtc_flush_all()
949 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_set() local
1012 crtc_flush(crtc, flush_mask); in mdp5_crtc_cursor_set()
1029 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); mdp5_crtc_cursor_move() local
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H A Dmdp5_mixer.h20 uint32_t flush_mask; /* used to commit LM registers */ member
H A Dmdp5_pipe.h23 uint32_t flush_mask; /* used to commit pipe registers */ member
H A Dmdp5_ctl.h64 * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
71 /* @flush_mask: see CTL flush masks definitions below */
73 u32 flush_mask, bool start);
H A Dmdp5_mixer.c165 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); in mdp5_mixer_init()
H A Dmdp5_pipe.c172 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); in mdp5_pipe_init()
H A Dmdp5_plane.c1071 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush()
1074 mask |= pstate->r_hwpipe->flush_mask; in mdp5_plane_get_flush()
/kernel/linux/linux-6.6/drivers/gpu/drm/msm/disp/mdp5/
H A Dmdp5_ctl.c37 /* pending flush_mask bits */
38 u32 flush_mask; member
473 u32 flush_mask) in fix_sw_flush()
478 (!(ctl_mgr->flush_hw_mask & bit) && (flush_mask & bit)) in fix_sw_flush()
487 static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask, in fix_for_single_flush() argument
493 DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask); in fix_for_single_flush()
495 ctl_mgr->single_flush_pending_mask |= (*flush_mask); in fix_for_single_flush()
496 *flush_mask = 0; in fix_for_single_flush()
500 *flush_mask = ctl_mgr->single_flush_pending_mask; in fix_for_single_flush()
506 DBG("Single FLUSH mask %x,ID %d", *flush_mask, in fix_for_single_flush()
472 fix_sw_flush(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask) fix_sw_flush() argument
535 mdp5_ctl_commit(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline, u32 flush_mask, bool start) mdp5_ctl_commit() argument
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H A Dmdp5_crtc.c90 static u32 crtc_flush(struct drm_crtc *crtc, u32 flush_mask) in crtc_flush() argument
99 DBG("%s: flush=%08x", crtc->name, flush_mask); in crtc_flush()
101 return mdp5_ctl_commit(ctl, pipeline, flush_mask, start); in crtc_flush()
114 uint32_t flush_mask = 0; in crtc_flush_all() local
123 flush_mask |= mdp5_plane_get_flush(plane); in crtc_flush_all()
127 flush_mask |= mdp_ctl_flush_mask_lm(mixer->lm); in crtc_flush_all()
131 flush_mask |= mdp_ctl_flush_mask_lm(r_mixer->lm); in crtc_flush_all()
133 return crtc_flush(crtc, flush_mask); in crtc_flush_all()
964 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); in mdp5_crtc_cursor_set() local
1027 crtc_flush(crtc, flush_mask); in mdp5_crtc_cursor_set()
1044 uint32_t flush_mask = mdp_ctl_flush_mask_cursor(0); mdp5_crtc_cursor_move() local
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H A Dmdp5_mixer.h20 uint32_t flush_mask; /* used to commit LM registers */ member
H A Dmdp5_pipe.h23 uint32_t flush_mask; /* used to commit pipe registers */ member
H A Dmdp5_ctl.h64 * through @flush_mask parameter in mdp5_ctl_commit(.., flush_mask).
71 /* @flush_mask: see CTL flush masks definitions below */
73 u32 flush_mask, bool start);
H A Dmdp5_mixer.c165 mixer->flush_mask = mdp_ctl_flush_mask_lm(lm->id); in mdp5_mixer_init()
H A Dmdp5_pipe.c172 hwpipe->flush_mask = mdp_ctl_flush_mask_pipe(pipe); in mdp5_pipe_init()
H A Dmdp5_plane.c1002 mask = pstate->hwpipe->flush_mask; in mdp5_plane_get_flush()
1005 mask |= pstate->r_hwpipe->flush_mask; in mdp5_plane_get_flush()
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/disp/dpu1/
H A Ddpu_crtc.c130 u32 flush_mask; in _dpu_crtc_blend_setup_mixer() local
143 dpu_plane_get_ctl_flush(plane, ctl, &flush_mask); in _dpu_crtc_blend_setup_mixer()
174 mixer[lm_idx].flush_mask |= flush_mask; in _dpu_crtc_blend_setup_mixer()
204 mixer[i].flush_mask = 0; in _dpu_crtc_blend_setup()
221 mixer[i].flush_mask |= ctl->ops.get_bitmask_mixer(ctl, in _dpu_crtc_blend_setup()
225 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_blend_setup()
231 mixer[i].flush_mask); in _dpu_crtc_blend_setup()
474 mixer[i].flush_mask |= ctl->ops.get_bitmask_dspp(ctl, in _dpu_crtc_setup_cp_blocks()
478 ctl->ops.update_pending_flush(ctl, mixer[i].flush_mask); in _dpu_crtc_setup_cp_blocks()
[all...]
H A Ddpu_encoder_phys_vid.c432 u32 flush_mask = 0; in dpu_encoder_phys_vid_enable() local
455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->hw_intf->idx); in dpu_encoder_phys_vid_enable()
456 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_vid_enable()
467 "update pending flush ctl %d flush_mask 0%x intf_mask 0x%x\n", in dpu_encoder_phys_vid_enable()
468 ctl->idx - CTL_0, flush_mask, intf_flush_mask); in dpu_encoder_phys_vid_enable()
H A Ddpu_crtc.h78 * @flush_mask: mixer flush mask for ctl, mixer and pipe
85 u32 flush_mask; member
H A Ddpu_encoder_phys_cmd.c440 u32 flush_mask = 0; in dpu_encoder_phys_cmd_enable_helper() local
455 ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx); in dpu_encoder_phys_cmd_enable_helper()
456 ctl->ops.update_pending_flush(ctl, flush_mask); in dpu_encoder_phys_cmd_enable_helper()
/kernel/linux/linux-6.6/drivers/net/wireless/mediatek/mt76/mt7603/
H A Dmac.c183 u32 flush_mask; in mt7603_filter_tx() local
199 flush_mask = MT_WF_ARB_TX_FLUSH_AC0 | in mt7603_filter_tx()
203 flush_mask <<= mac_idx; in mt7603_filter_tx()
205 mt76_wr(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask); in mt7603_filter_tx()
206 mt76_poll(dev, MT_WF_ARB_TX_FLUSH_0, flush_mask, 0, 20000); in mt7603_filter_tx()
207 mt76_wr(dev, MT_WF_ARB_TX_START_0, flush_mask); in mt7603_filter_tx()
/kernel/linux/linux-6.6/drivers/infiniband/hw/irdma/
H A Dhw.c2717 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask) in irdma_flush_wqes() argument
2723 if (!(flush_mask & IRDMA_FLUSH_SQ) && !(flush_mask & IRDMA_FLUSH_RQ)) in irdma_flush_wqes()
2727 info.sq = flush_mask & IRDMA_FLUSH_SQ; in irdma_flush_wqes()
2728 info.rq = flush_mask & IRDMA_FLUSH_RQ; in irdma_flush_wqes()
2737 if (flush_mask & IRDMA_REFLUSH) { in irdma_flush_wqes()
2757 flush_mask & IRDMA_FLUSH_WAIT); in irdma_flush_wqes()
H A Dmain.h475 void irdma_flush_wqes(struct irdma_qp *iwqp, u32 flush_mask);

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