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Searched refs:feature_mask (Results 1 - 25 of 94) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c320 uint32_t *feature_mask, in smu_cmn_get_enabled_mask()
327 if (!feature_mask || num < 2) in smu_cmn_get_enabled_mask()
339 feature_mask[0] = feature_mask_low; in smu_cmn_get_enabled_mask()
340 feature_mask[1] = feature_mask_high; in smu_cmn_get_enabled_mask()
342 bitmap_copy((unsigned long *)feature_mask, feature->enabled, in smu_cmn_get_enabled_mask()
350 uint64_t feature_mask, in smu_cmn_feature_update_enable_state()
359 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
365 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
372 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
378 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
319 smu_cmn_get_enabled_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) smu_cmn_get_enabled_mask() argument
349 smu_cmn_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled) smu_cmn_feature_update_enable_state() argument
433 uint32_t feature_mask[2] = { 0 }; smu_cmn_get_pp_feature_mask() local
483 uint32_t feature_mask[2] = { 0 }; smu_cmn_set_pp_feature_mask() local
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H A Dsmu_cmn.h52 uint32_t *feature_mask,
56 uint64_t feature_mask,
H A Dsmu_internal.h75 #define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/
H A Dsmu_cmn.c589 uint64_t *feature_mask) in smu_cmn_get_enabled_mask()
595 if (!feature_mask) in smu_cmn_get_enabled_mask()
598 feature_mask_low = &((uint32_t *)feature_mask)[0]; in smu_cmn_get_enabled_mask()
599 feature_mask_high = &((uint32_t *)feature_mask)[1]; in smu_cmn_get_enabled_mask()
645 uint64_t feature_mask, in smu_cmn_feature_update_enable_state()
653 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
659 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
664 lower_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
670 upper_32_bits(feature_mask), in smu_cmn_feature_update_enable_state()
712 uint64_t feature_mask; in smu_cmn_get_pp_feature_mask() local
588 smu_cmn_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) smu_cmn_get_enabled_mask() argument
644 smu_cmn_feature_update_enable_state(struct smu_context *smu, uint64_t feature_mask, bool enabled) smu_cmn_feature_update_enable_state() argument
757 uint64_t feature_mask; smu_cmn_set_pp_feature_mask() local
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H A Dsmu_cmn.h75 uint64_t *feature_mask);
82 uint64_t feature_mask,
H A Dsmu_internal.h75 #define smu_get_allowed_feature_mask(smu, feature_mask, num) smu_ppt_funcs(get_allowed_feature_mask, 0, smu, feature_mask, num)
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr.c106 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
117 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
122 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
127 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
135 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
140 hwmgr->feature_mask &= ~ (PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
148 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
153 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
164 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
174 hwmgr->feature_mask in hwmgr_early_init()
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H A Dvega10_hwmgr.c121 hwmgr->feature_mask & PP_SCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
123 hwmgr->feature_mask & PP_SOCCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
125 hwmgr->feature_mask & PP_MCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
127 hwmgr->feature_mask & PP_PCIE_DPM_MASK ? false : true; in vega10_set_default_registry_data()
130 hwmgr->feature_mask & PP_DCEFCLK_DPM_MASK ? false : true; in vega10_set_default_registry_data()
132 if (hwmgr->feature_mask & PP_POWER_CONTAINMENT_MASK) { in vega10_set_default_registry_data()
139 hwmgr->feature_mask & PP_CLOCK_STRETCH_MASK ? true : false; in vega10_set_default_registry_data()
142 hwmgr->feature_mask & PP_ULV_MASK ? true : false; in vega10_set_default_registry_data()
145 hwmgr->feature_mask & PP_SCLK_DEEP_SLEEP_MASK ? true : false; in vega10_set_default_registry_data()
154 hwmgr->feature_mask in vega10_set_default_registry_data()
2893 uint32_t i, feature_mask = 0; vega10_stop_dpm() local
2932 uint32_t i, feature_mask = 0; vega10_start_dpm() local
5464 uint32_t feature_mask = 0; vega10_disable_power_features_for_compute_performance() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/hwmgr/
H A Dhwmgr.c102 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
113 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
118 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
123 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
131 hwmgr->feature_mask &= ~PP_VBI_TIME_SUPPORT_MASK; in hwmgr_early_init()
136 hwmgr->feature_mask &= ~(PP_VBI_TIME_SUPPORT_MASK | in hwmgr_early_init()
144 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
149 hwmgr->feature_mask &= ~(PP_UVD_HANDSHAKE_MASK); in hwmgr_early_init()
160 hwmgr->feature_mask &= ~PP_GFXOFF_MASK; in hwmgr_early_init()
170 hwmgr->feature_mask in hwmgr_early_init()
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/kernel/linux/linux-6.6/drivers/thermal/intel/int340x_thermal/
H A Dprocessor_thermal_device.c319 kernel_ulong_t feature_mask) in proc_thermal_mmio_add()
323 proc_priv->mmio_feature_mask = feature_mask; in proc_thermal_mmio_add()
325 if (feature_mask) { in proc_thermal_mmio_add()
331 if (feature_mask & PROC_THERMAL_FEATURE_RAPL) { in proc_thermal_mmio_add()
339 if (feature_mask & PROC_THERMAL_FEATURE_FIVR || in proc_thermal_mmio_add()
340 feature_mask & PROC_THERMAL_FEATURE_DVFS || in proc_thermal_mmio_add()
341 feature_mask & PROC_THERMAL_FEATURE_DLVR) { in proc_thermal_mmio_add()
349 if (feature_mask & PROC_THERMAL_FEATURE_MBOX) { in proc_thermal_mmio_add()
317 proc_thermal_mmio_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv, kernel_ulong_t feature_mask) proc_thermal_mmio_add() argument
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu13/
H A Dsmu_v13_0_7_ppt.c258 uint32_t *feature_mask, uint32_t num) in smu_v13_0_7_get_allowed_feature_mask()
265 memset(feature_mask, 0, sizeof(uint32_t) * num); in smu_v13_0_7_get_allowed_feature_mask()
267 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FW_DATA_READ_BIT); in smu_v13_0_7_get_allowed_feature_mask()
270 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
271 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_IMU_BIT); in smu_v13_0_7_get_allowed_feature_mask()
272 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFX_POWER_OPTIMIZER_BIT); in smu_v13_0_7_get_allowed_feature_mask()
276 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in smu_v13_0_7_get_allowed_feature_mask()
279 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
280 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT); in smu_v13_0_7_get_allowed_feature_mask()
281 *(uint64_t *)feature_mask | in smu_v13_0_7_get_allowed_feature_mask()
257 smu_v13_0_7_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) smu_v13_0_7_get_allowed_feature_mask() argument
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/kernel/linux/linux-5.10/arch/arm64/kernel/
H A Dalternative.c136 unsigned long *feature_mask) in __apply_alternatives()
146 if (!test_bit(alt->cpufeature, feature_mask)) in __apply_alternatives()
189 feature_mask, ARM64_NCAPS); in __apply_alternatives()
135 __apply_alternatives(void *alt_region, bool is_module, unsigned long *feature_mask) __apply_alternatives() argument
/kernel/linux/linux-5.10/drivers/mfd/
H A Dkempld-core.c67 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
69 pld->feature_mask = 0; in kempld_get_info_generic()
97 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/kernel/linux/linux-6.6/drivers/mfd/
H A Dkempld-core.c67 pld->feature_mask = kempld_read16(pld, KEMPLD_FEATURE); in kempld_get_info_generic()
69 pld->feature_mask = 0; in kempld_get_info_generic()
97 if (pld->feature_mask & KEMPLD_FEATURE_BIT_I2C) in kempld_register_cells_generic()
100 if (pld->feature_mask & KEMPLD_FEATURE_BIT_WATCHDOG) in kempld_register_cells_generic()
103 if (pld->feature_mask & KEMPLD_FEATURE_BIT_GPIO) in kempld_register_cells_generic()
106 if (pld->feature_mask & KEMPLD_FEATURE_MASK_UART) in kempld_register_cells_generic()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dnavi10_ppt.c256 uint32_t *feature_mask, uint32_t num) in navi10_get_allowed_feature_mask()
263 memset(feature_mask, 0, sizeof(uint32_t) * num); in navi10_get_allowed_feature_mask()
265 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_PREFETCHER_BIT) in navi10_get_allowed_feature_mask()
287 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
290 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_LINK_BIT); in navi10_get_allowed_feature_mask()
293 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCEFCLK_BIT); in navi10_get_allowed_feature_mask()
296 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFX_ULV_BIT); in navi10_get_allowed_feature_mask()
299 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT); in navi10_get_allowed_feature_mask()
302 *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_GFXOFF_BIT); in navi10_get_allowed_feature_mask()
305 *(uint64_t *)feature_mask | in navi10_get_allowed_feature_mask()
255 navi10_get_allowed_feature_mask(struct smu_context *smu, uint32_t *feature_mask, uint32_t num) navi10_get_allowed_feature_mask() argument
1364 uint32_t feature_mask[2]; navi10_is_dpm_running() local
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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
H A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
H A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H A Dvega12_smumgr.h52 bool enable, uint64_t feature_mask);
H A Dvega10_smumgr.h46 bool enable, uint32_t feature_mask);
H A Dvega20_smumgr.h51 bool enable, uint64_t feature_mask);
/kernel/linux/linux-6.6/drivers/pci/msi/
H A Dirqdomain.c319 * @feature_mask: The feature mask to check for (full match)
324 bool pci_msi_domain_supports(struct pci_dev *pdev, unsigned int feature_mask, in pci_msi_domain_supports() argument
355 return (supported & feature_mask) == feature_mask; in pci_msi_domain_supports()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/swsmu/smu11/
H A Dcyan_skillfish_ppt.c566 uint64_t *feature_mask) in cyan_skillfish_get_enabled_mask()
568 if (!feature_mask) in cyan_skillfish_get_enabled_mask()
570 memset(feature_mask, 0xff, sizeof(*feature_mask)); in cyan_skillfish_get_enabled_mask()
565 cyan_skillfish_get_enabled_mask(struct smu_context *smu, uint64_t *feature_mask) cyan_skillfish_get_enabled_mask() argument
/kernel/linux/linux-6.6/drivers/net/
H A Dtap.c956 netdev_features_t feature_mask = 0; in set_offload() local
965 feature_mask = NETIF_F_HW_CSUM; in set_offload()
969 feature_mask |= NETIF_F_TSO_ECN; in set_offload()
971 feature_mask |= NETIF_F_TSO; in set_offload()
973 feature_mask |= NETIF_F_TSO6; in set_offload()
989 if (feature_mask & (NETIF_F_TSO | NETIF_F_TSO6) || in set_offload()
990 (feature_mask & (TUN_F_USO4 | TUN_F_USO6)) == (TUN_F_USO4 | TUN_F_USO6)) in set_offload()
998 tap->tap_features = feature_mask; in set_offload()
/kernel/linux/linux-6.6/include/sound/sof/
H A Dext_manifest4.h74 uint32_t feature_mask; member

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