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Searched refs:dwbc_mask (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb_cm.c44 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask in dwb3_get_reg_field_ogam()
[all...]
H A Ddcn30_dwb.c41 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
240 const struct dcn30_dwbc_mask *dwbc_mask, in dcn30_dwbc_construct()
250 dwbc30->dwbc_mask = dwbc_mask; in dcn30_dwbc_construct()
236 dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30, struct dc_context *ctx, const struct dcn30_dwbc_registers *dwbc_regs, const struct dcn30_dwbc_shift *dwbc_shift, const struct dcn30_dwbc_mask *dwbc_mask, int inst) dcn30_dwbc_construct() argument
H A Ddcn30_dwb.h879 const struct dcn30_dwbc_mask *dwbc_mask; member
886 const struct dcn30_dwbc_mask *dwbc_mask,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dwb_cm.c44 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
53 reg->masks.field_region_start_base = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_START_BASE_B; in dwb3_get_reg_field_ogam()
55 reg->masks.field_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_OFFSET_B; in dwb3_get_reg_field_ogam()
58 reg->masks.exp_region0_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_LUT_OFFSET; in dwb3_get_reg_field_ogam()
60 reg->masks.exp_region0_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION0_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
62 reg->masks.exp_region1_lut_offset = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_LUT_OFFSET; in dwb3_get_reg_field_ogam()
64 reg->masks.exp_region1_num_segments = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION1_NUM_SEGMENTS; in dwb3_get_reg_field_ogam()
67 reg->masks.field_region_end = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_B; in dwb3_get_reg_field_ogam()
69 reg->masks.field_region_end_slope = dwbc30->dwbc_mask->DWB_OGAM_RAMA_EXP_REGION_END_SLOPE_B; in dwb3_get_reg_field_ogam()
71 reg->masks.field_region_end_base = dwbc30->dwbc_mask in dwb3_get_reg_field_ogam()
[all...]
H A Ddcn30_dwb.c41 dwbc30->dwbc_shift->field_name, dwbc30->dwbc_mask->field_name
240 const struct dcn30_dwbc_mask *dwbc_mask, in dcn30_dwbc_construct()
250 dwbc30->dwbc_mask = dwbc_mask; in dcn30_dwbc_construct()
236 dcn30_dwbc_construct(struct dcn30_dwbc *dwbc30, struct dc_context *ctx, const struct dcn30_dwbc_registers *dwbc_regs, const struct dcn30_dwbc_shift *dwbc_shift, const struct dcn30_dwbc_mask *dwbc_mask, int inst) dcn30_dwbc_construct() argument
H A Ddcn30_dwb.h864 const struct dcn30_dwbc_mask *dwbc_mask; member
871 const struct dcn30_dwbc_mask *dwbc_mask,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.c42 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
120 const struct dcn10_dwbc_mask *dwbc_mask, in dcn10_dwbc_construct()
130 dwbc10->dwbc_mask = dwbc_mask; in dcn10_dwbc_construct()
116 dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, struct dc_context *ctx, const struct dcn10_dwbc_registers *dwbc_regs, const struct dcn10_dwbc_shift *dwbc_shift, const struct dcn10_dwbc_mask *dwbc_mask, int inst) dcn10_dwbc_construct() argument
H A Ddcn10_dwb.h259 const struct dcn10_dwbc_mask *dwbc_mask; member
266 const struct dcn10_dwbc_mask *dwbc_mask,
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H A Ddcn10_dwb.c40 dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name
118 const struct dcn10_dwbc_mask *dwbc_mask, in dcn10_dwbc_construct()
128 dwbc10->dwbc_mask = dwbc_mask; in dcn10_dwbc_construct()
114 dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, struct dc_context *ctx, const struct dcn10_dwbc_registers *dwbc_regs, const struct dcn10_dwbc_shift *dwbc_shift, const struct dcn10_dwbc_mask *dwbc_mask, int inst) dcn10_dwbc_construct() argument
H A Ddcn10_dwb.h257 const struct dcn10_dwbc_mask *dwbc_mask; member
264 const struct dcn10_dwbc_mask *dwbc_mask,
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c43 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
320 const struct dcn20_dwbc_mask *dwbc_mask, in dcn20_dwbc_construct()
330 dwbc20->dwbc_mask = dwbc_mask; in dcn20_dwbc_construct()
316 dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20, struct dc_context *ctx, const struct dcn20_dwbc_registers *dwbc_regs, const struct dcn20_dwbc_shift *dwbc_shift, const struct dcn20_dwbc_mask *dwbc_mask, int inst) dcn20_dwbc_construct() argument
H A Ddcn20_dwb.h419 const struct dcn20_dwbc_mask *dwbc_mask; member
426 const struct dcn20_dwbc_mask *dwbc_mask,
H A Ddcn20_dwb_scl.c44 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dwb.c43 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name
320 const struct dcn20_dwbc_mask *dwbc_mask, in dcn20_dwbc_construct()
330 dwbc20->dwbc_mask = dwbc_mask; in dcn20_dwbc_construct()
316 dcn20_dwbc_construct(struct dcn20_dwbc *dwbc20, struct dc_context *ctx, const struct dcn20_dwbc_registers *dwbc_regs, const struct dcn20_dwbc_shift *dwbc_shift, const struct dcn20_dwbc_mask *dwbc_mask, int inst) dcn20_dwbc_construct() argument
H A Ddcn20_dwb.h392 const struct dcn20_dwbc_mask *dwbc_mask; member
399 const struct dcn20_dwbc_mask *dwbc_mask,
H A Ddcn20_dwb_scl.c44 dwbc20->dwbc_shift->field_name, dwbc20->dwbc_mask->field_name

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