| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 51 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
58 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
134 uint32_t dppclk; member
156 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
163 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/ |
| H A D | clk_mgr.h | 50 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
57 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
66 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
73 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
158 uint32_t dppclk; member
181 uint32_t CLK1_CLK1_CURRENT_CNT; //dppclk
188 uint32_t CLK1_CLK1_BYPASS_CNTL; //dppclk bypass
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| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/calcs/ |
| H A D | dcn_calc_auto.c | 320 /*maximum dispclk/dppclk support check*/ in mode_support_and_system_configuration()
1179 /*dispclk and dppclk calculation*/ in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1300 v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1312 v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1423 v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1426 v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1654 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1655 v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all...] |
| H A D | dcn_calcs.c | 145 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
146 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
147 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
148 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
493 input.clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
1076 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */ in dcn_validate_bandwidth()
1699 "max_dchub_topscl_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1700 "max_pscl_tolb_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1701 "max_lb_tovscl_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1702 "max_vscl_tohscl_throughput: %d pixels/dppclk\ in dcn_bw_sync_calcs_and_dml()
[all...] |
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/calcs/ |
| H A D | dcn_calc_auto.c | 320 /*maximum dispclk/dppclk support check*/ in mode_support_and_system_configuration()
1179 /*dispclk and dppclk calculation*/ in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1223 v->dppclk = v->dispclk / v->dispclk_dppclk_ratio; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1300 v->display_pipe_line_delivery_time_luma[k] = v->swath_width_y[k] / v->pscl_throughput[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1312 v->display_pipe_line_delivery_time_chroma[k] = v->swath_width_y[k] / 2.0 / v->pscl_throughput_chroma[k] / v->dppclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1423 v->effective_det_plus_lb_lines_luma =dcn_bw_floor2(v->lines_in_dety[k] +dcn_bw_min2(v->lines_in_dety[k] * v->dppclk * v->byte_per_pixel_dety[k] * v->pscl_throughput[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_luma), v->swath_height_y[k]); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1426 v->effective_det_plus_lb_lines_chroma =dcn_bw_floor2(v->lines_in_detc[k] +dcn_bw_min2(v->lines_in_detc[k] * v->dppclk * v->byte_per_pixel_detc[k] * v->pscl_throughput_chroma[k] / (v->return_bw / v->dpp_per_plane[k]), v->effective_lb_latency_hiding_source_lines_chroma), v->swath_height_c[k]); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1643 v->dstx_after_scaler = 90.0 * v->pixel_clock[k] / v->dppclk + 42.0 * v->pixel_clock[k] / v->dispclk; in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1654 v->total_repeater_delay_time = v->max_inter_dcn_tile_repeaters * (2.0 / v->dppclk + 3.0 / v->dispclk); in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
1655 v->v_update_width_pix[k] = (14.0 / v->dcf_clk_deep_sleep + 12.0 / v->dppclk in dispclkdppclkdcfclk_deep_sleep_prefetch_parameters_watermarks_and_performance_calculation()
[all...] |
| H A D | dcn_calcs.c | 145 .max_dchub_topscl_throughput = 4, /*pixels/dppclk*/
146 .max_pscl_tolb_throughput = 2, /*pixels/dppclk*/
147 .max_lb_tovscl_throughput = 4, /*pixels/dppclk*/
148 .max_vscl_tohscl_throughput = 4, /*pixels/dppclk*/
496 input->clks_cfg.dppclk_mhz = v->dppclk; in dcn_bw_calc_rq_dlg_ttu()
1061 /* Unhack dppclk: dont bother with trying to pipe split if we cannot maintain dpm0 */ in dcn_validate_bandwidth()
1651 "max_dchub_topscl_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1652 "max_pscl_tolb_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1653 "max_lb_tovscl_throughput: %d pixels/dppclk\n" in dcn_bw_sync_calcs_and_dml()
1654 "max_vscl_tohscl_throughput: %d pixels/dppclk\ in dcn_bw_sync_calcs_and_dml()
[all...] |
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 297 uint32_t dppclk : 1; member
|
| H A D | dcn_calcs.h | 436 float dppclk; member
604 int max_dchub_topscl_throughput; /*pixels/dppclk*/
605 int max_pscl_tolb_throughput; /*pixels/dppclk*/
606 int max_lb_tovscl_throughput; /*pixels/dppclk*/
607 int max_vscl_tohscl_throughput; /*pixels/dppclk*/
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/ |
| H A D | core_types.h | 349 uint32_t dppclk : 1; member
|
| H A D | dcn_calcs.h | 436 float dppclk; member
604 int max_dchub_topscl_throughput; /*pixels/dppclk*/
605 int max_pscl_tolb_throughput; /*pixels/dppclk*/
606 int max_lb_tovscl_throughput; /*pixels/dppclk*/
607 int max_vscl_tohscl_throughput; /*pixels/dppclk*/
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.c | 1242 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1303 /* Detect dppclk change */ in dcn20_detect_pipe_changes()
1305 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1381 if (pipe_ctx->update_flags.bits.dppclk) in dcn20_update_dchubp_dpp()
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 161 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. in rn_update_clocks()
162 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result in rn_update_clocks()
192 // increase per DPP DTO before lowering global dppclk in rn_update_clocks()
280 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in rn_dump_clk_registers()
366 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", in rn_dump_clk_registers()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/ |
| H A D | rn_clk_mgr.c | 185 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. in rn_update_clocks()
186 // Do not adjust dppclk if dppclk is 0 to avoid unexpected result in rn_update_clocks()
214 // increase per DPP DTO before lowering global dppclk with requested dppclk in rn_update_clocks()
320 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in rn_dump_clk_registers()
406 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", in rn_dump_clk_registers()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn301/ |
| H A D | vg_clk_mgr.c | 153 // workaround: Limit dppclk to 100Mhz to avoid lower eDP panel switch to plus 4K monitor underflow. in vg_update_clocks()
172 // increase per DPP DTO before lowering global dppclk in vg_update_clocks()
252 regs_and_bypass->dppclk = internal.CLK1_CLK1_CURRENT_CNT / 10; in vg_dump_clk_registers()
338 chars_printed = snprintf_count(log_info->pBuf, remaining_buffer, "CLK1_CLK1_CURRENT_CNT,%d,dppclk\n", in vg_dump_clk_registers()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/ |
| H A D | dcn20_hwseq.c | 1342 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1424 /* Detect dppclk change */ in dcn20_detect_pipe_changes()
1426 new_pipe->update_flags.bits.dppclk = 1; in dcn20_detect_pipe_changes()
1506 if (pipe_ctx->update_flags.bits.dppclk) in dcn20_update_dchubp_dpp()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/ |
| H A D | dcn32_clk_mgr.c | 639 * compare the current and new dppclk before calling this function. in dcn32_update_clocks()
718 //Get dppclk in khz in dcn32_dump_clk_registers()
719 regs_and_bypass->dppclk = (DENTIST_DIVIDER_RANGE_SCALE_FACTOR in dcn32_dump_clk_registers()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/ |
| H A D | dcn32_hwseq.c | 1390 phantom_pipe->update_flags.bits.dppclk = 1; in dcn32_apply_update_flags_for_phantom()
|