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Searched refs:dm_write_reg (Results 1 - 25 of 74) sorted by relevance

123

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_regamma_v.c70 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
99 dm_write_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
113 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); in configure_regamma_mode()
151 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, in regamma_config_regions_and_segments()
162 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
173 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
190 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
222 dm_write_reg( in regamma_config_regions_and_segments()
255 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
287 dm_write_reg(xfm_dc in regamma_config_regions_and_segments()
[all...]
H A Ddce110_opp_csc_v.c142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
178 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
196 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
214 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
232 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
256 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
274 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
292 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
310 dm_write_reg(ct in program_color_matrix_v()
[all...]
H A Ddce110_mem_input_v.c52 dm_write_reg( in set_flip_control()
73 dm_write_reg( in program_pri_addr_c()
87 dm_write_reg( in program_pri_addr_c()
109 dm_write_reg( in program_pri_addr_l()
123 dm_write_reg( in program_pri_addr_l()
159 dm_write_reg(mem_input110->base.ctx, in enable()
201 dm_write_reg( in program_tiling()
223 dm_write_reg( in program_tiling()
254 dm_write_reg( in program_size_and_rotation()
262 dm_write_reg( in program_size_and_rotation()
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H A Ddce110_timing_generator_v.c65 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
70 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
75 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
91 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
117 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc()
137 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_unblank_crtc()
266 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
275 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
298 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
320 dm_write_reg(ct in dce110_timing_generator_v_program_blanking()
[all...]
H A Ddce110_compressor.c92 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); in reset_lb_on_vblank()
109 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); in reset_lb_on_vblank()
160 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
167 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
172 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
178 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
182 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce110_compressor_power_up_fbc()
185 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce110_compressor_power_up_fbc()
208 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_enable_fbc()
219 dm_write_reg(compresso in dce110_compressor_enable_fbc()
[all...]
H A Ddce110_transform_v.c101 dm_write_reg(ctx, addr, value); in program_viewport()
115 dm_write_reg(ctx, addr, value); in program_viewport()
131 dm_write_reg(ctx, addr, value); in program_viewport()
145 dm_write_reg(ctx, addr, value); in program_viewport()
175 dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value); in setup_scaling_configuration()
206 dm_write_reg(ctx, mmSCLV_MODE, value); in setup_scaling_configuration()
215 dm_write_reg(ctx, mmSCLV_CONTROL, value); in setup_scaling_configuration()
266 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
270 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
282 dm_write_reg(xfm_dc in set_coeff_update_complete()
[all...]
H A Ddce110_timing_generator.c116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
175 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_program_blank_color()
222 dm_write_reg(tg->ctx, addr, value);
225 dm_write_reg(tg->ctx, addr, value);
272 dm_write_reg(tg->ctx, in program_horz_count_by_2()
461 dm_write_reg(tg->ctx, addr, v_total_min); in dce110_timing_generator_set_drr()
464 dm_write_reg(tg->ctx, addr, v_total_max); in dce110_timing_generator_set_drr()
467 dm_write_reg(t in dce110_timing_generator_set_drr()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce110/
H A Ddce110_opp_regamma_v.c68 dm_write_reg(xfm->ctx, mmDCFEV_MEM_PWR_CTRL, value); in power_on_lut()
97 dm_write_reg(xfm_dce->base.ctx, in set_bypass_input_gamma()
111 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CONTROL, 0); in configure_regamma_mode()
149 dm_write_reg(xfm_dce->base.ctx, mmGAMMA_CORR_CNTLA_START_CNTL, in regamma_config_regions_and_segments()
160 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
171 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
188 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
220 dm_write_reg( in regamma_config_regions_and_segments()
253 dm_write_reg(xfm_dce->base.ctx, in regamma_config_regions_and_segments()
285 dm_write_reg(xfm_dc in regamma_config_regions_and_segments()
[all...]
H A Ddce110_opp_csc_v.c142 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
160 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
178 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
196 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
214 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
232 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
256 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
274 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
292 dm_write_reg(ctx, addr, value); in program_color_matrix_v()
310 dm_write_reg(ct in program_color_matrix_v()
[all...]
H A Ddce110_mem_input_v.c53 dm_write_reg( in set_flip_control()
74 dm_write_reg( in program_pri_addr_c()
88 dm_write_reg( in program_pri_addr_c()
110 dm_write_reg( in program_pri_addr_l()
124 dm_write_reg( in program_pri_addr_l()
160 dm_write_reg(mem_input110->base.ctx, in enable()
202 dm_write_reg( in program_tiling()
224 dm_write_reg( in program_tiling()
255 dm_write_reg( in program_size_and_rotation()
263 dm_write_reg( in program_size_and_rotation()
[all...]
H A Ddce110_timing_generator_v.c64 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
69 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
74 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
90 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
116 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_blank_crtc()
136 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_v_unblank_crtc()
265 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
274 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
297 dm_write_reg(ctx, addr, value); in dce110_timing_generator_v_program_blanking()
319 dm_write_reg(ct in dce110_timing_generator_v_program_blanking()
[all...]
H A Ddce110_compressor.c89 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); in reset_lb_on_vblank()
106 dm_write_reg(compressor->ctx, DCP_REG(mmLB_SYNC_RESET_SEL), value); in reset_lb_on_vblank()
157 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
164 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
169 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
175 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_power_up_fbc()
179 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce110_compressor_power_up_fbc()
182 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce110_compressor_power_up_fbc()
205 dm_write_reg(compressor->ctx, addr, value); in dce110_compressor_enable_fbc()
216 dm_write_reg(compresso in dce110_compressor_enable_fbc()
[all...]
H A Ddce110_transform_v.c99 dm_write_reg(ctx, addr, value); in program_viewport()
113 dm_write_reg(ctx, addr, value); in program_viewport()
129 dm_write_reg(ctx, addr, value); in program_viewport()
143 dm_write_reg(ctx, addr, value); in program_viewport()
173 dm_write_reg(ctx, mmSCLV_TAP_CONTROL, value); in setup_scaling_configuration()
204 dm_write_reg(ctx, mmSCLV_MODE, value); in setup_scaling_configuration()
213 dm_write_reg(ctx, mmSCLV_CONTROL, value); in setup_scaling_configuration()
263 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
267 dm_write_reg(xfm_dce->base.ctx, in program_overscan()
279 dm_write_reg(xfm_dc in set_coeff_update_complete()
[all...]
H A Ddce110_timing_generator.c116 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
140 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_MODE), value); in dce110_timing_generator_enable_crtc()
144 dm_write_reg(tg->ctx, CRTC_REG(mmCRTC_MASTER_UPDATE_LOCK), value); in dce110_timing_generator_enable_crtc()
175 dm_write_reg(tg->ctx, addr, value); in dce110_timing_generator_program_blank_color()
222 dm_write_reg(tg->ctx, addr, value);
225 dm_write_reg(tg->ctx, addr, value);
271 dm_write_reg(tg->ctx, in program_horz_count_by_2()
460 dm_write_reg(tg->ctx, addr, v_total_min); in dce110_timing_generator_set_drr()
463 dm_write_reg(tg->ctx, addr, v_total_max); in dce110_timing_generator_set_drr()
466 dm_write_reg(t in dce110_timing_generator_set_drr()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c337 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
344 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
349 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
355 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
359 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce112_compressor_power_up_fbc()
362 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce112_compressor_power_up_fbc()
400 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
409 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
411 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
427 dm_write_reg(compresso in dce112_compressor_disable_fbc()
[all...]
H A Ddce112_hw_sequencer.c109 dm_write_reg(ctx, addr, value); in dce112_init_pte()
141 dm_write_reg(ctx, in dce112_enable_display_power_gating()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce112/
H A Ddce112_compressor.c334 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
341 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
346 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
352 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_power_up_fbc()
356 dm_write_reg(compressor->ctx, mmFBC_IND_LUT0, value); in dce112_compressor_power_up_fbc()
359 dm_write_reg(compressor->ctx, mmFBC_IND_LUT1, value); in dce112_compressor_power_up_fbc()
397 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
406 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
408 dm_write_reg(compressor->ctx, addr, value); in dce112_compressor_enable_fbc()
424 dm_write_reg(compresso in dce112_compressor_disable_fbc()
[all...]
H A Ddce112_hw_sequencer.c109 dm_write_reg(ctx, addr, value); in dce112_init_pte()
138 dm_write_reg(ctx, in dce112_enable_display_power_gating()
/kernel/linux/linux-5.10/drivers/net/usb/
H A Ddm9601.c89 static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value) in dm_write_reg() function
116 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_read_shared_word()
117 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0xc : 0x4); in dm_read_shared_word()
138 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_read_shared_word()
159 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_write_shared_word()
160 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0x1a : 0x12); in dm_write_shared_word()
181 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_write_shared_word()
385 dm_write_reg(dev, DM_NET_CTRL, 1); in dm9601_bind()
422 dm_write_reg(dev, DM_MODE_CTRL, mode & 0x7f); in dm9601_bind()
426 dm_write_reg(de in dm9601_bind()
[all...]
/kernel/linux/linux-6.6/drivers/net/usb/
H A Ddm9601.c89 static int dm_write_reg(struct usbnet *dev, u8 reg, u8 value) in dm_write_reg() function
117 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_read_shared_word()
118 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0xc : 0x4); in dm_read_shared_word()
139 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_read_shared_word()
160 dm_write_reg(dev, DM_SHARED_ADDR, phy ? (reg | 0x40) : reg); in dm_write_shared_word()
161 dm_write_reg(dev, DM_SHARED_CTRL, phy ? 0x1a : 0x12); in dm_write_shared_word()
182 dm_write_reg(dev, DM_SHARED_CTRL, 0x0); in dm_write_shared_word()
386 dm_write_reg(dev, DM_NET_CTRL, 1); in dm9601_bind()
423 dm_write_reg(dev, DM_MODE_CTRL, mode & 0x7f); in dm9601_bind()
427 dm_write_reg(de in dm9601_bind()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.c250 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dce_dmcu_setup_psr()
262 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dce_dmcu_setup_psr()
267 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dce_dmcu_setup_psr()
315 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dce_psr_wait_loop()
689 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_dmcu_setup_psr()
701 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dcn10_dmcu_setup_psr()
706 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dcn10_dmcu_setup_psr()
741 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dcn10_psr_wait_loop()
963 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_forward_crc_window()
966 dm_write_reg(dmc in dcn10_forward_crc_window()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
174 dm_write_reg(tg->ctx, addr, value); in dce60_timing_generator_enable_advanced_request()
175 dm_write_reg(tg->ctx, addr2, value2); in dce60_timing_generator_enable_advanced_request()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dce60/
H A Ddce60_timing_generator.c105 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
174 dm_write_reg(tg->ctx, addr, value); in dce60_timing_generator_enable_advanced_request()
175 dm_write_reg(tg->ctx, addr2, value2); in dce60_timing_generator_enable_advanced_request()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce/
H A Ddce_dmcu.c246 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dce_dmcu_setup_psr()
258 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dce_dmcu_setup_psr()
263 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dce_dmcu_setup_psr()
311 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dce_psr_wait_loop()
685 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_dmcu_setup_psr()
697 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG2), in dcn10_dmcu_setup_psr()
702 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG3), in dcn10_dmcu_setup_psr()
737 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dcn10_psr_wait_loop()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dce120/
H A Ddce120_hw_sequencer.c110 dm_write_reg(ctx, addr, value);*/
145 dm_write_reg(ctx, addr, value);
180 dm_write_reg(ctx, in dce120_enable_display_power_gating()

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