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/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-pllv3.c37 * @div_mask: mask of divider bits
51 u32 div_mask; member
114 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
142 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
162 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
197 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
219 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
284 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
352 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
375 val &= ~pll->div_mask; /* clea in clk_pllv3_vf610_set_rate()
410 imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) imx_clk_hw_pllv3() argument
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H A Dclk-fixup-div.c12 #define div_mask(d) ((1 << (d->width)) - 1) macro
66 if (value > div_mask(div)) in clk_fixup_div_set_rate()
67 value = div_mask(div); in clk_fixup_div_set_rate()
72 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-pllv3.c38 * @div_mask: mask of divider bits
52 u32 div_mask; member
115 u32 div = (readl_relaxed(pll->base) >> pll->div_shift) & pll->div_mask; in clk_pllv3_recalc_rate()
143 val &= ~(pll->div_mask << pll->div_shift); in clk_pllv3_set_rate()
163 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_sys_recalc_rate()
198 val &= ~pll->div_mask; in clk_pllv3_sys_set_rate()
220 u32 div = readl_relaxed(pll->base) & pll->div_mask; in clk_pllv3_av_recalc_rate()
285 val &= ~pll->div_mask; in clk_pllv3_av_set_rate()
353 mf.mfi = (readl_relaxed(pll->base) & pll->div_mask) ? 22 : 20; in clk_pllv3_vf610_recalc_rate()
376 val &= ~pll->div_mask; /* clea in clk_pllv3_vf610_set_rate()
411 imx_clk_hw_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) imx_clk_hw_pllv3() argument
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H A Dclk-fixup-div.c12 #define div_mask(d) ((1 << (d->width)) - 1) macro
66 if (value > div_mask(div)) in clk_fixup_div_set_rate()
67 value = div_mask(div); in clk_fixup_div_set_rate()
72 val &= ~(div_mask(div) << div->shift); in clk_fixup_div_set_rate()
/kernel/linux/linux-5.10/drivers/clk/rockchip/
H A Dclk-half-divider.c11 #define div_mask(width) ((1 << (width)) - 1) macro
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
88 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
/kernel/linux/linux-6.6/drivers/clk/rockchip/
H A Dclk-half-divider.c11 #define div_mask(width) ((1 << (width)) - 1) macro
29 val &= div_mask(divider->width); in clk_half_divider_recalc_rate()
46 maxdiv = div_mask(width); in clk_half_divider_bestdiv()
88 bestdiv = div_mask(width); in clk_half_divider_bestdiv()
118 value = min_t(unsigned int, value, div_mask(divider->width)); in clk_half_divider_set_rate()
126 val = div_mask(divider->width) << (divider->shift + 16); in clk_half_divider_set_rate()
129 val &= ~(div_mask(divider->width) << divider->shift); in clk_half_divider_set_rate()
/kernel/linux/linux-5.10/drivers/clk/tegra/
H A Dclk-utils.c10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
H A Dclk-divider.c15 #define div_mask(d) ((1 << (d->width)) - 1) macro
17 #define get_max_div(d) div_mask(d)
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
/kernel/linux/linux-6.6/drivers/clk/tegra/
H A Dclk-utils.c10 #define div_mask(w) ((1 << (w)) - 1) macro
39 if (divider_ux1 > div_mask(width)) in div_frac_get()
40 return div_mask(width); in div_frac_get()
H A Dclk-divider.c15 #define div_mask(d) ((1 << (d->width)) - 1) macro
17 #define get_max_div(d) div_mask(d)
49 div = (reg >> divider->shift) & div_mask(divider); in clk_frac_div_recalc_rate()
96 val &= ~(div_mask(divider) << divider->shift); in clk_frac_div_set_rate()
/kernel/linux/linux-6.6/sound/soc/mediatek/mt8192/
H A Dmt8192-afe-clk.c412 int div_mask; member
427 .div_mask = APLL12_CK_DIV0_MASK,
440 .div_mask = APLL12_CK_DIV1_MASK,
453 .div_mask = APLL12_CK_DIV2_MASK,
466 .div_mask = APLL12_CK_DIV3_MASK,
479 .div_mask = APLL12_CK_DIV4_MASK,
492 .div_mask = APLL12_CK_DIVB_MASK,
502 .div_mask = APLL12_CK_DIV5_MASK,
515 .div_mask = APLL12_CK_DIV6_MASK,
528 .div_mask
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/kernel/linux/linux-5.10/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c19 #define div_mask(width) ((1 << (width)) - 1) macro
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
117 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
/kernel/linux/linux-6.6/drivers/clk/hisilicon/
H A Dclkdivider-hi6220.c19 #define div_mask(width) ((1 << (width)) - 1) macro
52 val &= div_mask(dclk->width); in hi6220_clkdiv_recalc_rate()
82 data &= ~(div_mask(dclk->width) << dclk->shift); in hi6220_clkdiv_set_rate()
117 max_div = div_mask(width) + 1; in hi6220_register_clkdiv()
/kernel/linux/linux-5.10/drivers/clk/
H A Dclk-vt8500.c23 unsigned int div_mask; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
126 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
169 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
181 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
262 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
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/kernel/linux/linux-5.10/drivers/i2c/busses/
H A Di2c-brcmstb.c94 u32 div_mask; member
126 .div_mask = 0
131 .div_mask = 0
136 .div_mask = 0
141 .div_mask = 0
146 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
151 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
156 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
161 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
555 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
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/kernel/linux/linux-6.6/drivers/clk/
H A Dclk-vt8500.c23 unsigned int div_mask; member
118 u32 div = readl(cdev->div_reg) & cdev->div_mask; in vt8500_dclk_recalc_rate()
121 if ((cdev->div_mask == 0x3F) && (div & BIT(5))) in vt8500_dclk_recalc_rate()
126 div = (cdev->div_mask + 1); in vt8500_dclk_recalc_rate()
150 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_round_rate()
169 if (divisor == cdev->div_mask + 1) in vt8500_dclk_set_rate()
173 if ((cdev->div_mask == 0x3F) && (divisor > 31)) { in vt8500_dclk_set_rate()
181 if (divisor > cdev->div_mask) { in vt8500_dclk_set_rate()
262 dev_clk->div_mask = 0x1f; in vtwm_device_clk_init()
264 of_property_read_u32(node, "divisor-mask", &dev_clk->div_mask); in vtwm_device_clk_init()
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/kernel/linux/linux-6.6/drivers/i2c/busses/
H A Di2c-brcmstb.c83 u32 div_mask; member
115 .div_mask = 0
120 .div_mask = 0
125 .div_mask = 0
130 .div_mask = 0
135 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
140 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
145 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
150 .div_mask = BSC_CTL_REG_DIV_CLK_MASK
544 bsc_clk[i].div_mask); in brcmstb_i2c_set_bus_speed()
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/kernel/linux/linux-5.10/drivers/clk/actions/
H A Dowl-factor.c158 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
193 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
194 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
198 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
/kernel/linux/linux-5.10/include/linux/
H A Dsh_clk.h60 unsigned int div_mask; member
157 .div_mask = SH_CLK_DIV4_MSK, \
181 .div_mask = SH_CLK_DIV6_MSK, \
193 .div_mask = SH_CLK_DIV6_MSK, \
/kernel/linux/linux-6.6/include/linux/
H A Dsh_clk.h60 unsigned int div_mask; member
157 .div_mask = SH_CLK_DIV4_MSK, \
181 .div_mask = SH_CLK_DIV6_MSK, \
193 .div_mask = SH_CLK_DIV6_MSK, \
/kernel/linux/linux-6.6/drivers/clk/actions/
H A Dowl-factor.c157 val &= div_mask(factor_hw); in owl_factor_helper_recalc_rate()
192 if (val > div_mask(factor_hw)) in owl_factor_helper_set_rate()
193 val = div_mask(factor_hw); in owl_factor_helper_set_rate()
197 reg &= ~(div_mask(factor_hw) << factor_hw->shift); in owl_factor_helper_set_rate()
/kernel/linux/linux-6.6/sound/soc/fsl/
H A Dfsl_mqs.c44 * @div_mask: clock divider mask
56 int div_mask; member
96 mqs_priv->soc->div_mask, in fsl_mqs_hw_params()
317 .div_mask = MQS_CLK_DIV_MASK,
330 .div_mask = IMX6SX_GPR2_MQS_CLK_DIV_MASK,
343 .div_mask = GENMASK(15, 8),
/kernel/linux/linux-5.10/drivers/clk/samsung/
H A Dclk-cpu.c230 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
252 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
255 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
340 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
351 exynos5433_set_safe_div(base, div, div_mask); in exynos5433_cpuclk_post_rate_change()
/kernel/linux/linux-6.6/drivers/clk/samsung/
H A Dclk-cpu.c230 unsigned long div = 0, div_mask = DIV_MASK; in exynos_cpuclk_post_rate_change() local
252 div_mask |= E4210_DIV0_ATB_MASK; in exynos_cpuclk_post_rate_change()
255 exynos_set_safe_div(base, div, div_mask); in exynos_cpuclk_post_rate_change()
340 unsigned long div = 0, div_mask = DIV_MASK; in exynos5433_cpuclk_post_rate_change() local
351 exynos5433_set_safe_div(base, div, div_mask); in exynos5433_cpuclk_post_rate_change()
/kernel/linux/linux-5.10/drivers/clk/mmp/
H A Dclk-mix.c29 unsigned int div_mask = (1 << mix->reg_info.width_div) - 1; in _get_maxdiv() local
34 return div_mask; in _get_maxdiv()
36 return 1 << div_mask; in _get_maxdiv()
43 return div_mask + 1; in _get_maxdiv()

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