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/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4.c693 uint32_t sec_count, ded_count; in gfx_v9_4_query_utc_edc_status() local
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
720 if (ded_count) { in gfx_v9_4_query_utc_edc_status()
723 vml2_mems[i], ded_count); in gfx_v9_4_query_utc_edc_status()
724 err_data->ue_count += ded_count; in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
743 if (ded_count) { in gfx_v9_4_query_utc_edc_status()
746 vml2_walker_mems[i], ded_count); in gfx_v9_4_query_utc_edc_status()
747 err_data->ue_count += ded_count; in gfx_v9_4_query_utc_edc_status()
763 ded_count in gfx_v9_4_query_utc_edc_status()
827 gfx_v9_4_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_4_ras_error_count() argument
870 uint32_t sec_count = 0, ded_count = 0; gfx_v9_4_query_ras_error_count() local
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H A Dmmhub_v1_0.c710 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) in mmhub_v1_0_get_ras_error_count()
738 *ded_count += ded_cnt; in mmhub_v1_0_get_ras_error_count()
749 uint32_t sec_count = 0, ded_count = 0; in mmhub_v1_0_query_ras_error_count() local
762 reg_value, &sec_count, &ded_count); in mmhub_v1_0_query_ras_error_count()
766 err_data->ue_count += ded_count; in mmhub_v1_0_query_ras_error_count()
708 mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) mmhub_v1_0_get_ras_error_count() argument
H A Dmmhub_v9_4.c1560 uint32_t *ded_count) in mmhub_v9_4_get_ras_error_count()
1586 *ded_count += ded_cnt; in mmhub_v9_4_get_ras_error_count()
1597 uint32_t sec_count = 0, ded_count = 0; in mmhub_v9_4_query_ras_error_count() local
1609 reg_value, &sec_count, &ded_count); in mmhub_v9_4_query_ras_error_count()
1613 err_data->ue_count += ded_count; in mmhub_v9_4_query_ras_error_count()
1556 mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) mmhub_v9_4_get_ras_error_count() argument
H A Dgfx_v9_0.c6467 uint32_t sec_count, ded_count; in gfx_v9_0_query_utc_edc_status() local
6489 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); in gfx_v9_0_query_utc_edc_status()
6490 if (ded_count) { in gfx_v9_0_query_utc_edc_status()
6492 "DED %d\n", i, vml2_mems[i], ded_count); in gfx_v9_0_query_utc_edc_status()
6493 err_data->ue_count += ded_count; in gfx_v9_0_query_utc_edc_status()
6509 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, in gfx_v9_0_query_utc_edc_status()
6511 if (ded_count) { in gfx_v9_0_query_utc_edc_status()
6513 "DED %d\n", i, vml2_walker_mems[i], ded_count); in gfx_v9_0_query_utc_edc_status()
6514 err_data->ue_count += ded_count; in gfx_v9_0_query_utc_edc_status()
6543 ded_count in gfx_v9_0_query_utc_edc_status()
6560 gfx_v9_0_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_0_ras_error_count() argument
6661 uint32_t sec_count = 0, ded_count = 0; gfx_v9_0_query_ras_error_count() local
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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_4.c693 uint32_t sec_count, ded_count; in gfx_v9_4_query_utc_edc_status() local
719 ded_count = REG_GET_FIELD(data, VML2_MEM_ECC_CNTL, DED_COUNT); in gfx_v9_4_query_utc_edc_status()
720 if (ded_count) { in gfx_v9_4_query_utc_edc_status()
723 vml2_mems[i], ded_count); in gfx_v9_4_query_utc_edc_status()
724 err_data->ue_count += ded_count; in gfx_v9_4_query_utc_edc_status()
741 ded_count = REG_GET_FIELD(data, VML2_WALKER_MEM_ECC_CNTL, in gfx_v9_4_query_utc_edc_status()
743 if (ded_count) { in gfx_v9_4_query_utc_edc_status()
746 vml2_walker_mems[i], ded_count); in gfx_v9_4_query_utc_edc_status()
747 err_data->ue_count += ded_count; in gfx_v9_4_query_utc_edc_status()
763 ded_count in gfx_v9_4_query_utc_edc_status()
827 gfx_v9_4_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_4_ras_error_count() argument
870 uint32_t sec_count = 0, ded_count = 0; gfx_v9_4_query_ras_error_count() local
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H A Dgfx_v9_4_2.c1456 uint32_t *ded_count) in gfx_v9_4_2_get_reg_error_count()
1484 *ded_count += ded_cnt; in gfx_v9_4_2_get_reg_error_count()
1492 uint32_t *sec_count, uint32_t *ded_count) in gfx_v9_4_2_query_sram_edc_count()
1497 if (sec_count && ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1499 *ded_count = 0; in gfx_v9_4_2_query_sram_edc_count()
1510 /* if sec/ded_count is null, just clear counter */ in gfx_v9_4_2_query_sram_edc_count()
1511 if (!sec_count || !ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1534 if (sec_count && ded_count) { in gfx_v9_4_2_query_sram_edc_count()
1536 *ded_count += ded_cnt; in gfx_v9_4_2_query_sram_edc_count()
1598 uint32_t *ded_count) in gfx_v9_4_2_query_utc_edc_count()
1452 gfx_v9_4_2_get_reg_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_4_2_get_reg_error_count() argument
1491 gfx_v9_4_2_query_sram_edc_count(struct amdgpu_device *adev, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_4_2_query_sram_edc_count() argument
1596 gfx_v9_4_2_query_utc_edc_count(struct amdgpu_device *adev, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_4_2_query_utc_edc_count() argument
1651 uint32_t sec_count = 0, ded_count = 0; gfx_v9_4_2_query_ras_error_count() local
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H A Dmmhub_v1_0.c710 uint32_t value, uint32_t *sec_count, uint32_t *ded_count) in mmhub_v1_0_get_ras_error_count()
738 *ded_count += ded_cnt; in mmhub_v1_0_get_ras_error_count()
749 uint32_t sec_count = 0, ded_count = 0; in mmhub_v1_0_query_ras_error_count() local
762 reg_value, &sec_count, &ded_count); in mmhub_v1_0_query_ras_error_count()
766 err_data->ue_count += ded_count; in mmhub_v1_0_query_ras_error_count()
708 mmhub_v1_0_get_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) mmhub_v1_0_get_ras_error_count() argument
H A Dmmhub_v1_7.c1210 uint32_t *ded_count) in mmhub_v1_7_get_ras_error_count()
1236 *ded_count += ded_cnt; in mmhub_v1_7_get_ras_error_count()
1247 uint32_t sec_count = 0, ded_count = 0; in mmhub_v1_7_query_ras_error_count() local
1259 reg_value, &sec_count, &ded_count); in mmhub_v1_7_query_ras_error_count()
1263 err_data->ue_count += ded_count; in mmhub_v1_7_query_ras_error_count()
1206 mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) mmhub_v1_7_get_ras_error_count() argument
H A Dmmhub_v9_4.c1565 uint32_t *ded_count) in mmhub_v9_4_get_ras_error_count()
1591 *ded_count += ded_cnt; in mmhub_v9_4_get_ras_error_count()
1602 uint32_t sec_count = 0, ded_count = 0; in mmhub_v9_4_query_ras_error_count() local
1614 reg_value, &sec_count, &ded_count); in mmhub_v9_4_query_ras_error_count()
1618 err_data->ue_count += ded_count; in mmhub_v9_4_query_ras_error_count()
1561 mmhub_v9_4_get_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) mmhub_v9_4_get_ras_error_count() argument
H A Dgfx_v9_0.c6540 uint32_t sec_count, ded_count; in gfx_v9_0_query_utc_edc_status() local
6562 ded_count = REG_GET_FIELD(data, VM_L2_MEM_ECC_CNT, DED_COUNT); in gfx_v9_0_query_utc_edc_status()
6563 if (ded_count) { in gfx_v9_0_query_utc_edc_status()
6565 "DED %d\n", i, vml2_mems[i], ded_count); in gfx_v9_0_query_utc_edc_status()
6566 err_data->ue_count += ded_count; in gfx_v9_0_query_utc_edc_status()
6582 ded_count = REG_GET_FIELD(data, VM_L2_WALKER_MEM_ECC_CNT, in gfx_v9_0_query_utc_edc_status()
6584 if (ded_count) { in gfx_v9_0_query_utc_edc_status()
6586 "DED %d\n", i, vml2_walker_mems[i], ded_count); in gfx_v9_0_query_utc_edc_status()
6587 err_data->ue_count += ded_count; in gfx_v9_0_query_utc_edc_status()
6616 ded_count in gfx_v9_0_query_utc_edc_status()
6633 gfx_v9_0_ras_error_count(struct amdgpu_device *adev, const struct soc15_reg_entry *reg, uint32_t se_id, uint32_t inst_id, uint32_t value, uint32_t *sec_count, uint32_t *ded_count) gfx_v9_0_ras_error_count() argument
6734 uint32_t sec_count = 0, ded_count = 0; gfx_v9_0_query_ras_error_count() local
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