Home
last modified time | relevance | path

Searched refs:dcn3_0_soc (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dml/dcn30/
H A Ddcn30_fpu.c125 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { variable
598 dcn3_0_soc.dram_channel_width_bytes = dc->ctx->dc_bios->vram_info.dram_channel_width_bytes; in dcn30_fpu_update_dram_channel_width_bytes()
606 dcn30_bb_max_clk->max_dcfclk_mhz = dcn3_0_soc.clock_limits[0].dcfclk_mhz; in dcn30_fpu_update_max_clk()
608 dcn30_bb_max_clk->max_dispclk_mhz = dcn3_0_soc.clock_limits[0].dispclk_mhz; in dcn30_fpu_update_max_clk()
610 dcn30_bb_max_clk->max_dppclk_mhz = dcn3_0_soc.clock_limits[0].dppclk_mhz; in dcn30_fpu_update_max_clk()
612 dcn30_bb_max_clk->max_phyclk_mhz = dcn3_0_soc.clock_limits[0].phyclk_mhz; in dcn30_fpu_update_max_clk()
623 bw_from_dram1 = uclk_mts * dcn3_0_soc.num_chans * in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
624 dcn3_0_soc.dram_channel_width_bytes * (dcn3_0_soc.max_avg_dram_bw_use_normal_percent / 100); in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
625 bw_from_dram2 = uclk_mts * dcn3_0_soc in dcn30_fpu_get_optimal_dcfclk_fclk_for_uclk()
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.c170 struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc = { variable
1715 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc; in init_soc_bounding_box()
1728 dcn3_0_soc.sr_exit_time_us = in init_soc_bounding_box()
1730 dcn3_0_soc.sr_enter_plus_exit_time_us = in init_soc_bounding_box()
1732 dcn3_0_soc.urgent_latency_us = in init_soc_bounding_box()
1734 dcn3_0_soc.urgent_latency_pixel_data_only_us = in init_soc_bounding_box()
1736 dcn3_0_soc.urgent_latency_pixel_mixed_with_vm_data_us = in init_soc_bounding_box()
1738 dcn3_0_soc.urgent_latency_vm_data_only_us = in init_soc_bounding_box()
1740 dcn3_0_soc.urgent_out_of_order_return_per_channel_pixel_only_bytes = in init_soc_bounding_box()
1742 dcn3_0_soc in init_soc_bounding_box()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_resource.h39 extern struct _vcs_dpi_soc_bounding_box_st dcn3_0_soc;
H A Ddcn30_resource.c1500 struct _vcs_dpi_soc_bounding_box_st *loaded_bb = &dcn3_0_soc; in init_soc_bounding_box()
1515 patch_dcn30_soc_bounding_box(dc, &dcn3_0_soc); in init_soc_bounding_box()
2108 dcn3_0_soc.num_chans = dc->ctx->dc_bios->vram_info.num_chans; in dcn30_update_bw_bounding_box()
2199 dcn3_0_soc.num_states = num_states; in dcn30_update_bw_bounding_box()
2428 dml_init_instance(&dc->dml, &dcn3_0_soc, &dcn3_0_ip, DML_PROJECT_DCN30); in dcn30_resource_construct()

Completed in 7 milliseconds