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Searched refs:dccg (Results 1 - 25 of 89) sorted by relevance

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/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h66 struct dccg { struct
88 void (*update_dpp_dto)(struct dccg *dccg,
91 void (*get_dccg_ref_freq)(struct dccg *dccg,
94 void (*set_fifo_errdet_ovr_en)(struct dccg *dccg,
96 void (*otg_add_pixel)(struct dccg *dccg,
98 void (*otg_drop_pixel)(struct dccg *dcc
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn31/
H A Ddcn31_dccg.c31 #define TO_DCN_DCCG(dccg)\
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 void dccg31_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg31_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg31_update_dpp_dto()
50 if (dccg->dpp_clock_gated[dpp_inst]) { in dccg31_update_dpp_dto()
58 if (dccg->ref_dppclk && req_dppclk) { in dccg31_update_dpp_dto()
59 int ref_dppclk = dccg->ref_dppclk; in dccg31_update_dpp_dto()
80 dccg in dccg31_update_dpp_dto()
97 dccg31_enable_dpstreamclk(struct dccg *dccg, int otg_inst) dccg31_enable_dpstreamclk() argument
129 dccg31_disable_dpstreamclk(struct dccg *dccg, int otg_inst) dccg31_disable_dpstreamclk() argument
161 dccg31_set_dpstreamclk( struct dccg *dccg, enum streamclk_source src, int otg_inst, int dp_hpo_inst) dccg31_set_dpstreamclk() argument
173 dccg31_enable_symclk32_se( struct dccg *dccg, int hpo_se_inst, enum phyd32clk_clock_source phyd32clk) dccg31_enable_symclk32_se() argument
226 dccg31_disable_symclk32_se( struct dccg *dccg, int hpo_se_inst) dccg31_disable_symclk32_se() argument
276 dccg31_enable_symclk32_le( struct dccg *dccg, int hpo_le_inst, enum phyd32clk_clock_source phyd32clk) dccg31_enable_symclk32_le() argument
303 dccg31_disable_symclk32_le( struct dccg *dccg, int hpo_le_inst) dccg31_disable_symclk32_le() argument
327 dccg31_set_symclk32_le_root_clock_gating( struct dccg *dccg, int hpo_le_inst, bool enable) dccg31_set_symclk32_le_root_clock_gating() argument
354 dccg31_disable_dscclk(struct dccg *dccg, int inst) dccg31_disable_dscclk() argument
398 dccg31_enable_dscclk(struct dccg *dccg, int inst) dccg31_enable_dscclk() argument
442 dccg31_set_physymclk( struct dccg *dccg, int phy_inst, enum physymclk_clock_source clk_src, bool force_enable) dccg31_set_physymclk() argument
544 dccg31_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) dccg31_set_dtbclk_dto() argument
610 dccg31_set_audio_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) dccg31_set_audio_dtbclk_dto() argument
642 dccg31_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz) dccg31_get_dccg_ref_freq() argument
654 dccg31_set_dispclk_change_mode( struct dccg *dccg, enum dentist_dispclk_change_mode change_mode) dccg31_set_dispclk_change_mode() argument
664 dccg31_init(struct dccg *dccg) dccg31_init() argument
694 dccg31_otg_add_pixel(struct dccg *dccg, uint32_t otg_inst) dccg31_otg_add_pixel() argument
703 dccg31_otg_drop_pixel(struct dccg *dccg, uint32_t otg_inst) dccg31_otg_drop_pixel() argument
[all...]
H A Ddcn31_dccg.h156 struct dccg *dccg31_create(
162 void dccg31_init(struct dccg *dccg);
165 struct dccg *dccg,
170 struct dccg *dccg,
174 struct dccg *dccg,
179 struct dccg *dcc
[all...]
H A Ddcn31_hwseq.c31 #include "dccg.h"
125 // Initialize the dccg in dcn31_init_hw()
126 if (res_pool->dccg->funcs->dccg_init) in dcn31_init_hw()
127 res_pool->dccg->funcs->dccg_init(res_pool->dccg); in dcn31_init_hw()
135 if (res_pool->dccg && res_pool->hubbub) { in dcn31_init_hw()
137 (res_pool->dccg->funcs->get_dccg_ref_freq)(res_pool->dccg, in dcn31_init_hw()
290 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn31_dsc_pg_control()
292 hws->ctx->dc->res_pool->dccg in dcn31_dsc_pg_control()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c32 #define TO_DCN_DCCG(dccg)\
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dcc argument
99 dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg, bool en) dccg2_set_fifo_errdet_ovr_en() argument
108 dccg2_otg_add_pixel(struct dccg *dccg, uint32_t otg_inst) dccg2_otg_add_pixel() argument
120 dccg2_otg_drop_pixel(struct dccg *dccg, uint32_t otg_inst) dccg2_otg_drop_pixel() argument
132 dccg2_init(struct dccg *dccg) dccg2_init() argument
170 dcn_dccg_destroy(struct dccg **dccg) dcn_dccg_destroy() argument
[all...]
H A Ddcn20_dccg.h29 #include "dccg.h"
298 struct dccg base;
304 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
306 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
310 void dccg2_set_fifo_errdet_ovr_en(struct dccg *dccg,
312 void dccg2_otg_add_pixel(struct dccg *dccg,
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn314/
H A Ddcn314_dccg.c33 #define TO_DCN_DCCG(dccg)\
34 container_of(dccg, struct dcn_dccg, base)
46 dccg->ctx->logger
49 struct dccg *dccg) in dccg314_trigger_dio_fifo_resync()
51 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg314_get_pixel_rate_div()
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg314_get_pixel_rate_div()
101 struct dccg *dcc in dccg314_set_pixel_rate_div()
48 dccg314_trigger_dio_fifo_resync( struct dccg *dccg) dccg314_trigger_dio_fifo_resync() argument
58 dccg314_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div *k1, enum pixel_rate_div *k2) dccg314_get_pixel_rate_div() argument
100 dccg314_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div k1, enum pixel_rate_div k2) dccg314_set_pixel_rate_div() argument
147 dccg314_set_dtbclk_p_src( struct dccg *dccg, enum streamclk_source src, uint32_t otg_inst) dccg314_set_dtbclk_p_src() argument
204 dccg314_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) dccg314_set_dtbclk_dto() argument
248 dccg314_set_dpstreamclk( struct dccg *dccg, enum streamclk_source src, int otg_inst, int dp_hpo_inst) dccg314_set_dpstreamclk() argument
287 dccg314_init(struct dccg *dccg) dccg314_init() argument
313 dccg314_set_valid_pixel_rate( struct dccg *dccg, int ref_dtbclk_khz, int otg_inst, int pixclk_khz) dccg314_set_valid_pixel_rate() argument
328 dccg314_dpp_root_clock_control( struct dccg *dccg, unsigned int dpp_inst, bool clock_on) dccg314_dpp_root_clock_control() argument
[all...]
H A Ddcn314_hwseq.c32 #include "dccg.h"
250 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc && in dcn314_dsc_pg_control()
252 hws->ctx->dc->res_pool->dccg->funcs->enable_dsc( in dcn314_dsc_pg_control()
253 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
301 if (hws->ctx->dc->res_pool->dccg->funcs->disable_dsc && !power_on) in dcn314_dsc_pg_control()
302 hws->ctx->dc->res_pool->dccg->funcs->disable_dsc( in dcn314_dsc_pg_control()
303 hws->ctx->dc->res_pool->dccg, dsc_inst); in dcn314_dsc_pg_control()
412 hws->ctx->dc->res_pool->dccg->funcs->trigger_dio_fifo_resync(hws->ctx->dc->res_pool->dccg); in dcn314_resync_fifo_dccg_dio()
427 if (hws->ctx->dc->res_pool->dccg in dcn314_dpp_root_clock_control()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn32/
H A Ddcn32_dccg.c30 #define TO_DCN_DCCG(dccg)\
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
46 struct dccg *dccg) in dccg32_trigger_dio_fifo_resync()
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_trigger_dio_fifo_resync()
59 struct dccg *dccg, in dccg32_get_pixel_rate_div()
64 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg32_get_pixel_rate_div()
101 struct dccg *dcc in dccg32_set_pixel_rate_div()
45 dccg32_trigger_dio_fifo_resync( struct dccg *dccg) dccg32_trigger_dio_fifo_resync() argument
58 dccg32_get_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div *k1, enum pixel_rate_div *k2) dccg32_get_pixel_rate_div() argument
100 dccg32_set_pixel_rate_div( struct dccg *dccg, uint32_t otg_inst, enum pixel_rate_div k1, enum pixel_rate_div k2) dccg32_set_pixel_rate_div() argument
148 dccg32_set_dtbclk_p_src( struct dccg *dccg, enum streamclk_source src, uint32_t otg_inst) dccg32_set_dtbclk_p_src() argument
204 dccg32_set_dtbclk_dto( struct dccg *dccg, const struct dtbclk_dto_params *params) dccg32_set_dtbclk_dto() argument
247 dccg32_set_valid_pixel_rate( struct dccg *dccg, int ref_dtbclk_khz, int otg_inst, int pixclk_khz) dccg32_set_valid_pixel_rate() argument
263 dccg32_get_dccg_ref_freq(struct dccg *dccg, unsigned int xtalin_freq_inKhz, unsigned int *dccg_ref_freq_inKhz) dccg32_get_dccg_ref_freq() argument
275 dccg32_set_dpstreamclk( struct dccg *dccg, enum streamclk_source src, int otg_inst, int dp_hpo_inst) dccg32_set_dpstreamclk() argument
312 dccg32_otg_add_pixel(struct dccg *dccg, uint32_t otg_inst) dccg32_otg_add_pixel() argument
321 dccg32_otg_drop_pixel(struct dccg *dccg, uint32_t otg_inst) dccg32_otg_drop_pixel() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H A Ddcn20_dccg.c32 #define TO_DCN_DCCG(dccg)\
33 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg2_update_dpp_dto() argument
49 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg2_update_dpp_dto()
51 if (dccg->ref_dppclk && req_dppclk) { in dccg2_update_dpp_dto()
52 int ref_dppclk = dccg->ref_dppclk; in dccg2_update_dpp_dto()
74 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg2_update_dpp_dto()
77 void dccg2_get_dccg_ref_freq(struct dccg *dcc argument
99 dccg2_init(struct dccg *dccg) dccg2_init() argument
134 dcn_dccg_destroy(struct dccg **dccg) dcn_dccg_destroy() argument
[all...]
H A Ddcn20_dccg.h29 #include "dccg.h"
116 struct dccg base;
122 void dccg2_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk);
124 void dccg2_get_dccg_ref_freq(struct dccg *dccg,
128 void dccg2_init(struct dccg *dccg);
130 struct dccg *dccg2_create(
136 void dcn_dccg_destroy(struct dccg **dcc
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn21/
H A Ddcn21_dccg.c31 #define TO_DCN_DCCG(dccg)\
32 container_of(dccg, struct dcn_dccg, base)
44 dccg->ctx->logger
46 static void dccg21_update_dpp_dto(struct dccg *dccg, int dpp_inst, int req_dppclk) in dccg21_update_dpp_dto() argument
48 struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg); in dccg21_update_dpp_dto()
50 if (dccg->ref_dppclk) { in dccg21_update_dpp_dto()
51 int ref_dppclk = dccg->ref_dppclk; in dccg21_update_dpp_dto()
96 dccg->pipe_dppclk_khz[dpp_inst] = req_dppclk; in dccg21_update_dpp_dto()
109 struct dccg *dccg21_creat
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/inc/hw/
H A Ddccg.h32 struct dccg { struct
40 void (*update_dpp_dto)(struct dccg *dccg,
43 void (*get_dccg_ref_freq)(struct dccg *dccg,
46 void (*dccg_init)(struct dccg *dccg);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn201/
H A Ddcn201_dccg.c31 #define TO_DCN_DCCG(dccg)\
32 container_of(dccg, struct dcn_dccg, base)
45 dccg->ctx->logger
47 static void dccg201_update_dpp_dto(struct dccg *dccg, int dpp_inst, in dccg201_update_dpp_dto() argument
62 struct dccg *dccg201_create( in dccg201_create()
69 struct dccg *base; in dccg201_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.c26 #include "dccg.h"
109 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn20_update_clocks_update_dpp_dto()
119 prev_dppclk_khz = clk_mgr->dccg->pipe_dppclk_khz[i]; in dcn20_update_clocks_update_dpp_dto()
122 clk_mgr->dccg->funcs->update_dpp_dto( in dcn20_update_clocks_update_dpp_dto()
123 clk_mgr->dccg, dpp_inst, dppclk_khz); in dcn20_update_clocks_update_dpp_dto()
155 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; in dcn20_update_clocks_update_dentist() local
168 dccg->funcs->set_fifo_errdet_ovr_en( in dcn20_update_clocks_update_dentist()
169 dccg, in dcn20_update_clocks_update_dentist()
185 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; dcn20_update_clocks_update_dentist() local
528 dcn20_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) dcn20_clk_mgr_construct() argument
[all...]
H A Ddcn20_clk_mgr.h29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.c30 #define TO_DCN_DCCG(dccg)\
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
52 struct dccg *dccg3_create( in dccg3_create()
59 struct dccg *base; in dccg3_create()
77 struct dccg *dccg30_create( in dccg30_create()
84 struct dccg *base; in dccg30_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn30/
H A Ddcn30_dccg.c30 #define TO_DCN_DCCG(dccg)\
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
55 struct dccg *dccg3_create( in dccg3_create()
62 struct dccg *base; in dccg3_create()
80 struct dccg *dccg30_create( in dccg30_create()
87 struct dccg *base; in dccg30_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c30 #include "dccg.h"
151 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
237 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
242 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
264 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
268 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
272 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
276 dcn201_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
279 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
[all...]
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn301/
H A Ddcn301_dccg.c30 #define TO_DCN_DCCG(dccg)\
31 container_of(dccg, struct dcn_dccg, base)
43 dccg->ctx->logger
54 struct dccg *dccg301_create( in dccg301_create()
61 struct dccg *base; in dccg301_create()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/
H A Dclk_mgr.c30 #include "dccg.h"
115 struct clk_mgr *dc_clk_mgr_create(struct dc_context *ctx, struct pp_smu_funcs *pp_smu, struct dccg *dccg) in dc_clk_mgr_create() argument
166 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
171 rn_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
188 dcn3_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
192 dcn20_clk_mgr_construct(ctx, clk_mgr, pp_smu, dccg); in dc_clk_mgr_create()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn32/
H A Ddcn32_clk_mgr.c26 #include "dccg.h"
249 struct dccg *dccg = clk_mgr->dccg; in dcn32_update_clocks_update_dtb_dto() local
265 dccg->funcs->set_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn32_update_clocks_update_dtb_dto()
266 //dccg->funcs->set_audio_dtbclk_dto(clk_mgr->dccg, &dto_params); in dcn32_update_clocks_update_dtb_dto()
298 clk_mgr->dccg->ref_dppclk = clk_mgr->base.clks.dppclk_khz; in dcn32_update_clocks_update_dpp_dto()
319 prev_dppclk_khz = clk_mgr->dccg in dcn32_update_clocks_update_dpp_dto()
353 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; dcn32_update_clocks_update_dentist() local
398 struct dccg *dccg = clk_mgr->base.ctx->dc->res_pool->dccg; dcn32_update_clocks_update_dentist() local
950 dcn32_clk_mgr_construct( struct dc_context *ctx, struct clk_mgr_internal *clk_mgr, struct pp_smu_funcs *pp_smu, struct dccg *dccg) dcn32_clk_mgr_construct() argument
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/
H A Ddcn20_clk_mgr.h29 void dcn2_update_clocks(struct clk_mgr *dccg,
44 struct dccg *dccg);
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/link/hwss/
H A Dlink_hwss_hpo_dp.c28 #include "dccg.h"
111 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in enable_hpo_dp_link_output()
112 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in enable_hpo_dp_link_output()
113 link->dc->res_pool->dccg, in enable_hpo_dp_link_output()
130 if (link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating) in disable_hpo_dp_link_output()
131 link->dc->res_pool->dccg->funcs->set_symclk32_le_root_clock_gating( in disable_hpo_dp_link_output()
132 link->dc->res_pool->dccg, in disable_hpo_dp_link_output()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/
H A Drn_clk_mgr.h39 struct dccg *dccg);

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