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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2/
H A Dprobe.c34 boot_cpu_data.dcache.ways = 4; in cpu_probe()
35 boot_cpu_data.dcache.way_incr = (1<<12); in cpu_probe()
36 boot_cpu_data.dcache.sets = 256; in cpu_probe()
37 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
38 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
39 boot_cpu_data.dcache.flags = 0; in cpu_probe()
56 boot_cpu_data.dcache.ways = 1; in cpu_probe()
57 boot_cpu_data.dcache.sets = 256; in cpu_probe()
58 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
59 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2/
H A Dprobe.c34 boot_cpu_data.dcache.ways = 4; in cpu_probe()
35 boot_cpu_data.dcache.way_incr = (1<<12); in cpu_probe()
36 boot_cpu_data.dcache.sets = 256; in cpu_probe()
37 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
38 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
39 boot_cpu_data.dcache.flags = 0; in cpu_probe()
56 boot_cpu_data.dcache.ways = 1; in cpu_probe()
57 boot_cpu_data.dcache.sets = 256; in cpu_probe()
58 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
59 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-5.10/arch/mips/mm/
H A Dc-octeon.c34 * Octeon automatically flushes the dcache on tlb changes, so
114 * dcache aliases don't need to do anything here in octeon_flush_cache_mm()
186 c->dcache.linesz = 128; in probe_octeon()
188 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
190 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
191 c->dcache.ways = 64; in probe_octeon()
193 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
194 c->dcache in probe_octeon()
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H A Dc-r4k.c591 * If dcache can alias, we must blast it since mapping is changing. in local_r4k_flush_cache_range()
1125 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1126 c->dcache.ways = 2; in probe_pcache()
1127 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1139 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1140 c->dcache.ways = 2; in probe_pcache()
1141 c->dcache.waybit = 0; in probe_pcache()
1153 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1154 c->dcache.ways = 4; in probe_pcache()
1155 c->dcache in probe_pcache()
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H A Dc-tx39.c303 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
304 current_cpu_data.dcache.linesz = 4; in tx39_probe_cache()
309 current_cpu_data.dcache.ways = 2; in tx39_probe_cache()
310 current_cpu_data.dcache.linesz = 16; in tx39_probe_cache()
316 current_cpu_data.dcache.ways = 1; in tx39_probe_cache()
317 current_cpu_data.dcache.linesz = 16; in tx39_probe_cache()
383 (dcache_size / current_cpu_data.dcache.ways) - 1, in tx39_cache_init()
393 current_cpu_data.dcache.waysize = dcache_size / current_cpu_data.dcache.ways; in tx39_cache_init()
397 current_cpu_data.dcache in tx39_cache_init()
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/kernel/linux/linux-6.6/arch/mips/mm/
H A Dc-octeon.c33 * Octeon automatically flushes the dcache on tlb changes, so
117 * dcache aliases don't need to do anything here in octeon_flush_cache_mm()
189 c->dcache.linesz = 128; in probe_octeon()
191 c->dcache.sets = 2; /* CN5XXX has two Dcache sets */ in probe_octeon()
193 c->dcache.sets = 1; /* CN3XXX has one Dcache set */ in probe_octeon()
194 c->dcache.ways = 64; in probe_octeon()
196 c->dcache.sets * c->dcache.ways * c->dcache.linesz; in probe_octeon()
197 c->dcache in probe_octeon()
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H A Dc-r4k.c479 * If dcache can alias, we must blast it since mapping is changing. in local_r4k_flush_cache_range()
1014 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1015 c->dcache.ways = 2; in probe_pcache()
1016 c->dcache.waybit= __ffs(dcache_size/2); in probe_pcache()
1028 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1029 c->dcache.ways = 2; in probe_pcache()
1030 c->dcache.waybit = 0; in probe_pcache()
1042 c->dcache.linesz = 16 << ((config & CONF_DB) >> 4); in probe_pcache()
1043 c->dcache.ways = 4; in probe_pcache()
1044 c->dcache in probe_pcache()
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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh3/
H A Dprobe.c50 boot_cpu_data.dcache.ways = 4; in cpu_probe()
51 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
52 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
53 boot_cpu_data.dcache.flags = 0; in cpu_probe()
60 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
61 boot_cpu_data.dcache.entry_mask = 0x7f0; in cpu_probe()
62 boot_cpu_data.dcache.sets = 128; in cpu_probe()
67 boot_cpu_data.dcache.way_incr = (1 << 12); in cpu_probe()
68 boot_cpu_data.dcache.entry_mask = 0xff0; in cpu_probe()
69 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh3/
H A Dprobe.c50 boot_cpu_data.dcache.ways = 4; in cpu_probe()
51 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
52 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
53 boot_cpu_data.dcache.flags = 0; in cpu_probe()
60 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
61 boot_cpu_data.dcache.entry_mask = 0x7f0; in cpu_probe()
62 boot_cpu_data.dcache.sets = 128; in cpu_probe()
67 boot_cpu_data.dcache.way_incr = (1 << 12); in cpu_probe()
68 boot_cpu_data.dcache.entry_mask = 0xff0; in cpu_probe()
69 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/
H A Dinit.c128 waysize = current_cpu_data.dcache.sets; in cache_init()
139 waysize <<= current_cpu_data.dcache.entry_shift; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
155 addr += current_cpu_data.dcache.linesz) in cache_init()
158 addrstart += current_cpu_data.dcache.way_incr; in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
204 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); in detect_cache_shape()
206 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) in detect_cache_shape()
313 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache in cpu_init()
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/kernel/linux/linux-6.6/arch/sh/kernel/cpu/
H A Dinit.c128 waysize = current_cpu_data.dcache.sets; in cache_init()
139 waysize <<= current_cpu_data.dcache.entry_shift; in cache_init()
147 ways = current_cpu_data.dcache.ways; in cache_init()
155 addr += current_cpu_data.dcache.linesz) in cache_init()
158 addrstart += current_cpu_data.dcache.way_incr; in cache_init()
170 if (current_cpu_data.dcache.ways > 1) in cache_init()
204 l1d_cache_shape = CACHE_DESC_SHAPE(current_cpu_data.dcache); in detect_cache_shape()
206 if (current_cpu_data.dcache.flags & SH_CACHE_COMBINED) in detect_cache_shape()
313 current_cpu_data.dcache.entry_mask = current_cpu_data.dcache in cpu_init()
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/kernel/linux/linux-5.10/arch/sh/mm/
H A Dcache-sh7705.c34 ways = current_cpu_data.dcache.ways; in cache_wback_all()
35 waysize = current_cpu_data.dcache.sets; in cache_wback_all()
36 waysize <<= current_cpu_data.dcache.entry_shift; in cache_wback_all()
45 addr += current_cpu_data.dcache.linesz) { in cache_wback_all()
56 addrstart += current_cpu_data.dcache.way_incr; in cache_wback_all()
102 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
103 waysize = current_cpu_data.dcache.sets; in __flush_dcache_page()
104 waysize <<= current_cpu_data.dcache.entry_shift; in __flush_dcache_page()
113 addr += current_cpu_data.dcache.linesz) { in __flush_dcache_page()
123 addrstart += current_cpu_data.dcache in __flush_dcache_page()
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H A Dcache.c64 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in copy_to_user_page()
71 if (boot_cpu_data.dcache.n_aliases) in copy_to_user_page()
83 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in copy_from_user_page()
90 if (boot_cpu_data.dcache.n_aliases) in copy_from_user_page()
102 if (boot_cpu_data.dcache.n_aliases && page_mapcount(from) && in copy_user_highpage()
142 if (!boot_cpu_data.dcache.n_aliases) in __update_cache()
158 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in __flush_anon_page()
179 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_mm()
187 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_dup_mm()
268 boot_cpu_data.dcache in emit_cache_params()
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H A Dcache-sh4.c24 * The maximum number of pages we support up to when doing ranged dcache
25 * flushing. Anything exceeding this will simply flush the dcache in its
153 (current_cpu_data.dcache.sets << in flush_dcache_all()
154 current_cpu_data.dcache.entry_shift) * in flush_dcache_all()
155 current_cpu_data.dcache.ways; in flush_dcache_all()
157 entry_offset = 1 << current_cpu_data.dcache.entry_shift; in flush_dcache_all()
237 map_coherent = (current_cpu_data.dcache.n_aliases && in sh4_flush_cache_page()
288 if (boot_cpu_data.dcache.n_aliases == 0) in sh4_flush_cache_range()
316 struct cache_info *dcache; in __flush_cache_one() local
321 dcache in __flush_cache_one()
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H A Dcache-sh3.c44 for (j = 0; j < current_cpu_data.dcache.ways; j++) { in sh3__flush_wback_region()
48 addr = addrstart | (v & current_cpu_data.dcache.entry_mask); in sh3__flush_wback_region()
60 addrstart += current_cpu_data.dcache.way_incr; in sh3__flush_wback_region()
85 (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; in sh3__flush_purge_region()
/kernel/linux/linux-6.6/arch/sh/mm/
H A Dcache-sh7705.c35 ways = current_cpu_data.dcache.ways; in cache_wback_all()
36 waysize = current_cpu_data.dcache.sets; in cache_wback_all()
37 waysize <<= current_cpu_data.dcache.entry_shift; in cache_wback_all()
46 addr += current_cpu_data.dcache.linesz) { in cache_wback_all()
57 addrstart += current_cpu_data.dcache.way_incr; in cache_wback_all()
103 ways = current_cpu_data.dcache.ways; in __flush_dcache_page()
104 waysize = current_cpu_data.dcache.sets; in __flush_dcache_page()
105 waysize <<= current_cpu_data.dcache.entry_shift; in __flush_dcache_page()
114 addr += current_cpu_data.dcache.linesz) { in __flush_dcache_page()
124 addrstart += current_cpu_data.dcache in __flush_dcache_page()
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H A Dcache.c66 if (boot_cpu_data.dcache.n_aliases && folio_mapped(folio) && in copy_to_user_page()
73 if (boot_cpu_data.dcache.n_aliases) in copy_to_user_page()
87 if (boot_cpu_data.dcache.n_aliases && page_mapcount(page) && in copy_from_user_page()
94 if (boot_cpu_data.dcache.n_aliases) in copy_from_user_page()
107 if (boot_cpu_data.dcache.n_aliases && folio_mapped(src) && in copy_user_highpage()
146 if (!boot_cpu_data.dcache.n_aliases) in __update_cache()
164 if (boot_cpu_data.dcache.n_aliases && folio_mapped(folio) && in __flush_anon_page()
186 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_mm()
194 if (boot_cpu_data.dcache.n_aliases == 0) in flush_cache_dup_mm()
276 boot_cpu_data.dcache in emit_cache_params()
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H A Dcache-sh4.c25 * The maximum number of pages we support up to when doing ranged dcache
26 * flushing. Anything exceeding this will simply flush the dcache in its
164 (current_cpu_data.dcache.sets << in flush_dcache_all()
165 current_cpu_data.dcache.entry_shift) * in flush_dcache_all()
166 current_cpu_data.dcache.ways; in flush_dcache_all()
168 entry_offset = 1 << current_cpu_data.dcache.entry_shift; in flush_dcache_all()
248 map_coherent = (current_cpu_data.dcache.n_aliases && in sh4_flush_cache_page()
299 if (boot_cpu_data.dcache.n_aliases == 0) in sh4_flush_cache_range()
327 struct cache_info *dcache; in __flush_cache_one() local
332 dcache in __flush_cache_one()
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H A Dcache-sh3.c44 for (j = 0; j < current_cpu_data.dcache.ways; j++) { in sh3__flush_wback_region()
48 addr = addrstart | (v & current_cpu_data.dcache.entry_mask); in sh3__flush_wback_region()
60 addrstart += current_cpu_data.dcache.way_incr; in sh3__flush_wback_region()
85 (v & current_cpu_data.dcache.entry_mask) | SH_CACHE_ASSOC; in sh3__flush_purge_region()
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh2a/
H A Dprobe.c43 boot_cpu_data.dcache.ways = 4; in cpu_probe()
44 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
45 boot_cpu_data.dcache.sets = 128; in cpu_probe()
46 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
47 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
48 boot_cpu_data.dcache.flags = 0; in cpu_probe()
51 * The icache is the same as the dcache as far as this setup is in cpu_probe()
53 * lacks the U bit that the dcache has, none of this has any bearing in cpu_probe()
56 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh2a/
H A Dprobe.c43 boot_cpu_data.dcache.ways = 4; in cpu_probe()
44 boot_cpu_data.dcache.way_incr = (1 << 11); in cpu_probe()
45 boot_cpu_data.dcache.sets = 128; in cpu_probe()
46 boot_cpu_data.dcache.entry_shift = 4; in cpu_probe()
47 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
48 boot_cpu_data.dcache.flags = 0; in cpu_probe()
51 * The icache is the same as the dcache as far as this setup is in cpu_probe()
53 * lacks the U bit that the dcache has, none of this has any bearing in cpu_probe()
56 boot_cpu_data.icache = boot_cpu_data.dcache; in cpu_probe()
/kernel/linux/linux-5.10/arch/sh/kernel/cpu/sh4/
H A Dprobe.c42 * And again for the dcache .. in cpu_probe()
44 boot_cpu_data.dcache.way_incr = (1 << 14); in cpu_probe()
45 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
46 boot_cpu_data.dcache.sets = 512; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
48 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-6.6/arch/sh/kernel/cpu/sh4/
H A Dprobe.c42 * And again for the dcache .. in cpu_probe()
44 boot_cpu_data.dcache.way_incr = (1 << 14); in cpu_probe()
45 boot_cpu_data.dcache.entry_shift = 5; in cpu_probe()
46 boot_cpu_data.dcache.sets = 512; in cpu_probe()
47 boot_cpu_data.dcache.ways = 1; in cpu_probe()
48 boot_cpu_data.dcache.linesz = L1_CACHE_BYTES; in cpu_probe()
68 boot_cpu_data.dcache.ways = 4; in cpu_probe()
172 boot_cpu_data.dcache.ways = 2; in cpu_probe()
177 boot_cpu_data.dcache.ways = 2; in cpu_probe()
193 boot_cpu_data.dcache in cpu_probe()
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/kernel/linux/linux-5.10/arch/mips/include/asm/
H A Dr4kcache.h250 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
253 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
257 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
260 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
264 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
265 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
283 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
286 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
289 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
312 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_
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/kernel/linux/linux-6.6/arch/mips/include/asm/
H A Dr4kcache.h240 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16, )
243 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32, )
247 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 64, )
250 __BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 128, )
254 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16, )
255 __BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32, )
273 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
276 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
279 __BUILD_BLAST_USER_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D,
300 __BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_
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