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/kernel/linux/linux-5.10/arch/loongarch/kvm/
H A Dcsr.c16 #define CASE_READ_SW_GCSR(csr, regid, csrid) \
19 return kvm_read_sw_gcsr(csr, csrid); \
25 struct loongarch_csrs *csr = vcpu->arch.csr; in _kvm_emu_read_csr() local
28 CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRCTL); in _kvm_emu_read_csr()
29 CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRINFO1); in _kvm_emu_read_csr()
30 CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRINFO2); in _kvm_emu_read_csr()
31 CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRENTRY); in _kvm_emu_read_csr()
32 CASE_READ_SW_GCSR(csr, csrid, KVM_CSR_MERRERA); in _kvm_emu_read_csr()
33 CASE_READ_SW_GCSR(csr, csri in _kvm_emu_read_csr()
65 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_emu_write_csr() local
104 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_emu_xchg_csr() local
128 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_getcsr() local
208 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_setcsr() local
[all...]
H A Dkvmcsr.h15 #define kvm_write_hw_gcsr(csr, id, val) gcsr_write(val, id)
25 static inline void kvm_save_hw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_save_hw_gcsr() argument
27 csr->csrs[gid] = gcsr_read(gid); in kvm_save_hw_gcsr()
30 static inline void kvm_restore_hw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_restore_hw_gcsr() argument
32 gcsr_write(csr->csrs[gid], gid); in kvm_restore_hw_gcsr()
35 static inline unsigned long kvm_read_sw_gcsr(struct loongarch_csrs *csr, int gid) in kvm_read_sw_gcsr() argument
37 return csr->csrs[gid]; in kvm_read_sw_gcsr()
40 static inline void kvm_write_sw_gcsr(struct loongarch_csrs *csr, int gid, unsigned long val) in kvm_write_sw_gcsr() argument
42 csr->csrs[gid] = val; in kvm_write_sw_gcsr()
45 static inline void kvm_set_sw_gcsr(struct loongarch_csrs *csr, in argument
50 kvm_change_sw_gcsr(struct loongarch_csrs *csr, int gid, unsigned mask, unsigned long val) kvm_change_sw_gcsr() argument
[all...]
H A Dloongarch.c624 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_arch_vcpu_create() local
640 vcpu->arch.csr = kzalloc(sizeof(struct loongarch_csrs), GFP_KERNEL); in kvm_arch_vcpu_create()
647 if (!vcpu->arch.csr) in kvm_arch_vcpu_create()
661 kvm_write_sw_gcsr(csr, KVM_CSR_CRMD, KVM_CRMD_DA); in kvm_arch_vcpu_create()
664 kvm_write_sw_gcsr(csr, KVM_CSR_TMID, vcpu->vcpu_id); in kvm_arch_vcpu_create()
667 csr->csrs[KVM_CSR_GINTC] = 0; in kvm_arch_vcpu_create()
682 kfree(vcpu->arch.csr); in kvm_arch_vcpu_destroy()
831 struct loongarch_csrs *csr = vcpu->arch.csr; in _kvm_vcpu_load() local
954 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_vcpu_put() local
1034 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_get_one_reg() local
1084 struct loongarch_csrs *csr = vcpu->arch.csr; _kvm_set_one_reg() local
1894 struct loongarch_csrs *csr; kvm_arch_vcpu_dump_regs() local
2132 struct loongarch_csrs *csr = vcpu->arch.csr; kvm_lose_hw_perf() local
2165 struct loongarch_csrs *csr = vcpu->arch.csr; kvm_restore_hw_perf() local
[all...]
H A Dtimer.c88 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_init_timer() local
100 kvm_write_sw_gcsr(csr, KVM_CSR_TVAL, ticks); in kvm_init_timer()
116 timer_cfg = kvm_read_sw_gcsr(vcpu->arch.csr, KVM_CSR_TCFG); in kvm_count_timeout()
132 struct loongarch_csrs *csr = vcpu->arch.csr; in kvm_restore_timer() local
140 * Set guest stable timer cfg csr in kvm_restore_timer()
142 timer_cfg = kvm_read_sw_gcsr(csr, KVM_CSR_TCFG); in kvm_restore_timer()
143 kvm_restore_hw_gcsr(csr, KVM_CSR_ESTAT); in kvm_restore_timer()
145 kvm_restore_hw_gcsr(csr, KVM_CSR_TCF in kvm_restore_timer()
240 struct loongarch_csrs *csr = vcpu->arch.csr; kvm_save_timer() local
[all...]
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/
H A Dintel_csr.c33 * DOC: csr support for dmc
302 u32 *payload = dev_priv->csr.dmc_payload; in intel_csr_load_program()
311 if (!dev_priv->csr.dmc_payload) { in intel_csr_load_program()
317 fw_size = dev_priv->csr.dmc_fw_size; in intel_csr_load_program()
328 for (i = 0; i < dev_priv->csr.mmio_count; i++) { in intel_csr_load_program()
329 intel_de_write(dev_priv, dev_priv->csr.mmioaddr[i], in intel_csr_load_program()
330 dev_priv->csr.mmiodata[i]); in intel_csr_load_program()
333 dev_priv->csr.dc_state = 0; in intel_csr_load_program()
382 static u32 parse_csr_fw_dmc(struct intel_csr *csr, in parse_csr_fw_dmc() argument
391 BUILD_BUG_ON(ARRAY_SIZE(csr in parse_csr_fw_dmc()
489 parse_csr_fw_package(struct intel_csr *csr, const struct intel_package_header *package_header, const struct stepping_info *si, size_t rem_size) parse_csr_fw_package() argument
548 parse_csr_fw_css(struct intel_csr *csr, struct intel_css_header *css_header, size_t rem_size) parse_csr_fw_css() argument
587 struct intel_csr *csr = &dev_priv->csr; parse_csr_fw() local
634 struct intel_csr *csr; csr_load_work_fn() local
672 struct intel_csr *csr = &dev_priv->csr; intel_csr_ucode_init() local
[all...]
/kernel/linux/linux-6.6/drivers/crypto/intel/qat/qat_common/
H A Dicp_qat_hw_20_comp.h23 ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_comp_20_config_csr_lower csr) in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER() argument
27 QAT_FIELD_SET(val32, csr.algo, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
30 QAT_FIELD_SET(val32, csr.sd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
33 QAT_FIELD_SET(val32, csr.edmm, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
36 QAT_FIELD_SET(val32, csr.hbs, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
39 QAT_FIELD_SET(val32, csr.lllbd, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
42 QAT_FIELD_SET(val32, csr.mmctrl, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
45 QAT_FIELD_SET(val32, csr.hash_col, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
48 QAT_FIELD_SET(val32, csr.hash_update, in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
51 QAT_FIELD_SET(val32, csr in ICP_QAT_FW_COMP_20_BUILD_CONFIG_LOWER()
74 ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_comp_20_config_csr_upper csr) ICP_QAT_FW_COMP_20_BUILD_CONFIG_UPPER() argument
121 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER(struct icp_qat_hw_decomp_20_config_csr_lower csr) ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_LOWER() argument
150 ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER(struct icp_qat_hw_decomp_20_config_csr_upper csr) ICP_QAT_FW_DECOMP_20_BUILD_CONFIG_UPPER() argument
[all...]
/kernel/linux/linux-5.10/arch/sparc/kernel/
H A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, in ebus_dma_register()
127 u32 csr; ebus_dma_irq_enable() local
159 u32 csr; ebus_dma_unregister() local
179 u32 csr; ebus_dma_request() local
208 u32 csr; ebus_dma_prepare() local
244 u32 orig_csr, csr; ebus_dma_enable() local
[all...]
/kernel/linux/linux-6.6/arch/sparc/kernel/
H A Debus.c74 u32 csr = 0; in ebus_dma_irq() local
77 csr = readl(p->regs + EBDMA_CSR); in ebus_dma_irq()
78 writel(csr, p->regs + EBDMA_CSR); in ebus_dma_irq()
81 if (csr & EBDMA_CSR_ERR_PEND) { in ebus_dma_irq()
85 } else if (csr & EBDMA_CSR_INT_PEND) { in ebus_dma_irq()
87 (csr & EBDMA_CSR_TC) ? in ebus_dma_irq()
99 u32 csr; in ebus_dma_register() local
113 csr = EBDMA_CSR_BURST_SZ_16 | EBDMA_CSR_EN_CNT; in ebus_dma_register()
116 csr |= EBDMA_CSR_TCI_DIS; in ebus_dma_register()
118 writel(csr, in ebus_dma_register()
127 u32 csr; ebus_dma_irq_enable() local
159 u32 csr; ebus_dma_unregister() local
179 u32 csr; ebus_dma_request() local
208 u32 csr; ebus_dma_prepare() local
244 u32 orig_csr, csr; ebus_dma_enable() local
[all...]
/kernel/linux/linux-5.10/arch/alpha/kernel/
H A Dcore_tsunami.c182 volatile unsigned long *csr; in tsunami_pci_tbi()
187 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
189 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
195 *csr = value; in tsunami_pci_tbi()
197 *csr; in tsunami_pci_tbi()
229 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
233 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
234 int source = (TSUNAMI_cchip->misc.csr >> 2 in tsunami_probe_write()
181 volatile unsigned long *csr; tsunami_pci_tbi() local
[all...]
H A Dcore_wildfire.c121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr in wildfire_init_hose()
[all...]
H A Dcore_titan.c210 volatile unsigned long *csr; in titan_pci_tbi()
223 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
225 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
232 *csr = value; in titan_pci_tbi()
234 *csr;
243 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
296 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
207 volatile unsigned long *csr; titan_pci_tbi() local
[all...]
/kernel/linux/linux-6.6/arch/alpha/kernel/
H A Dcore_tsunami.c182 volatile unsigned long *csr; in tsunami_pci_tbi()
187 csr = &pchip->tlbia.csr; in tsunami_pci_tbi()
189 csr = &pchip->tlbiv.csr; in tsunami_pci_tbi()
195 *csr = value; in tsunami_pci_tbi()
197 *csr; in tsunami_pci_tbi()
229 TSUNAMI_cchip->misc.csr |= (1L << 28); /* clear NXM... */ in tsunami_probe_write()
233 if (TSUNAMI_cchip->misc.csr & (1L << 28)) { in tsunami_probe_write()
234 int source = (TSUNAMI_cchip->misc.csr >> 2 in tsunami_probe_write()
181 volatile unsigned long *csr; tsunami_pci_tbi() local
[all...]
H A Dcore_wildfire.c121 pci->pci_window[0].wbase.csr = hose->sg_isa->dma_base | 3; in wildfire_init_hose()
122 pci->pci_window[0].wmask.csr = (hose->sg_isa->size - 1) & 0xfff00000; in wildfire_init_hose()
123 pci->pci_window[0].tbase.csr = virt_to_phys(hose->sg_isa->ptes); in wildfire_init_hose()
125 pci->pci_window[1].wbase.csr = 0x40000000 | 1; in wildfire_init_hose()
126 pci->pci_window[1].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
127 pci->pci_window[1].tbase.csr = 0; in wildfire_init_hose()
129 pci->pci_window[2].wbase.csr = 0x80000000 | 1; in wildfire_init_hose()
130 pci->pci_window[2].wmask.csr = (0x40000000 -1) & 0xfff00000; in wildfire_init_hose()
131 pci->pci_window[2].tbase.csr = 0x40000000; in wildfire_init_hose()
133 pci->pci_window[3].wbase.csr in wildfire_init_hose()
[all...]
H A Dcore_titan.c210 volatile unsigned long *csr; in titan_pci_tbi()
223 csr = &port->port_specific.g.gtlbia.csr; in titan_pci_tbi()
225 csr = &port->port_specific.g.gtlbiv.csr; in titan_pci_tbi()
232 *csr = value; in titan_pci_tbi()
234 *csr;
243 pctl.pctl_q_whole = port->pctl.csr; in titan_query_agp()
296 saved_config[index].wsba[0] = port->wsba[0].csr; in titan_init_one_pachip_port()
297 saved_config[index].wsm[0] = port->wsm[0].csr; in titan_init_one_pachip_port()
207 volatile unsigned long *csr; titan_pci_tbi() local
[all...]
/kernel/linux/linux-6.6/drivers/crypto/starfive/
H A Djh7110-rsa.c100 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
102 writel(rctx->csr.pka.v, cryp->base + STARFIVE_PKA_CACR_OFFSET); in starfive_rsa_montgomery_form()
108 rctx->csr.pka.v = 0; in starfive_rsa_montgomery_form()
109 rctx->csr.pka.cln_done = 1; in starfive_rsa_montgomery_form()
110 rctx->csr.pka.opsize = opsize; in starfive_rsa_montgomery_form()
111 rctx->csr.pka.exposize = opsize; in starfive_rsa_montgomery_form()
112 rctx->csr.pka.cmd = CRYPTO_CMD_PRE; in starfive_rsa_montgomery_form()
113 rctx->csr.pka.start = 1; in starfive_rsa_montgomery_form()
114 rctx->csr.pka.not_r2 = 1; in starfive_rsa_montgomery_form()
115 rctx->csr in starfive_rsa_montgomery_form()
[all...]
/kernel/linux/linux-5.10/drivers/usb/musb/
H A Dmusb_gadget_ep0.c243 u16 csr; variable
266 csr = musb_readw(regs, MUSB_TXCSR);
267 csr |= MUSB_TXCSR_CLRDATATOG |
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
272 musb_writew(regs, MUSB_TXCSR, csr);
274 csr = musb_readw(regs, MUSB_RXCSR);
275 csr |= MUSB_RXCSR_CLRDATATOG |
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
279 musb_writew(regs, MUSB_RXCSR, csr);
403 u16 csr; variable
465 u16 count, csr; ep0_rxstate() local
522 u16 csr = MUSB_CSR0_TXPKTRDY; ep0_txstate() local
643 u16 csr; musb_g_ep0_irq() local
997 u16 csr; musb_g_ep0_halt() local
[all...]
H A Dmusb_gadget.c229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
305 csr in txstate()
408 u16 csr; musb_g_tx() local
526 u16 csr = musb_readw(epio, MUSB_RXCSR); rxstate() local
792 u16 csr; musb_g_rx() local
918 u16 csr; musb_gadget_enable() local
1336 u16 csr; musb_gadget_set_halt() local
1457 u16 csr; musb_gadget_fifo_flush() local
[all...]
/kernel/linux/linux-6.6/drivers/usb/musb/
H A Dmusb_gadget_ep0.c243 u16 csr; variable
266 csr = musb_readw(regs, MUSB_TXCSR);
267 csr |= MUSB_TXCSR_CLRDATATOG |
269 csr &= ~(MUSB_TXCSR_P_SENDSTALL |
272 musb_writew(regs, MUSB_TXCSR, csr);
274 csr = musb_readw(regs, MUSB_RXCSR);
275 csr |= MUSB_RXCSR_CLRDATATOG |
277 csr &= ~(MUSB_RXCSR_P_SENDSTALL |
279 musb_writew(regs, MUSB_RXCSR, csr);
403 u16 csr; variable
465 u16 count, csr; ep0_rxstate() local
522 u16 csr = MUSB_CSR0_TXPKTRDY; ep0_txstate() local
643 u16 csr; musb_g_ep0_irq() local
997 u16 csr; musb_g_ep0_halt() local
[all...]
H A Dmusb_gadget.c229 u16 fifo_count = 0, csr; in txstate() local
248 csr = musb_readw(epio, MUSB_TXCSR); in txstate()
254 if (csr & MUSB_TXCSR_TXPKTRDY) { in txstate()
256 musb_ep->end_point.name, csr); in txstate()
260 if (csr & MUSB_TXCSR_P_SENDSTALL) { in txstate()
262 musb_ep->end_point.name, csr); in txstate()
268 csr); in txstate()
301 csr &= ~(MUSB_TXCSR_AUTOSET in txstate()
303 musb_writew(epio, MUSB_TXCSR, csr in txstate()
305 csr in txstate()
408 u16 csr; musb_g_tx() local
526 u16 csr = musb_readw(epio, MUSB_RXCSR); rxstate() local
792 u16 csr; musb_g_rx() local
918 u16 csr; musb_gadget_enable() local
1336 u16 csr; musb_gadget_set_halt() local
1457 u16 csr; musb_gadget_fifo_flush() local
[all...]
/kernel/linux/linux-5.10/drivers/crypto/qat/qat_common/
H A Dicp_qat_hal.h90 #define SET_CAP_CSR(handle, csr, val) \
91 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
92 #define GET_CAP_CSR(handle, csr) \
93 ADF_CSR_RD(handle->hal_cap_g_ctl_csr_addr_v, csr)
94 #define SET_GLB_CSR(handle, csr, val) SET_CAP_CSR(handle, csr + GLOBAL_CSR, val)
95 #define GET_GLB_CSR(handle, csr) GET_CAP_CSR(handle, GLOBAL_CSR + csr)
99 #define AE_CSR_ADDR(handle, ae, csr) (AE_CSR(handle, ae) + (0x3ff & csr))
[all...]
/kernel/linux/linux-5.10/drivers/watchdog/
H A Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr in sh_wdt_start()
128 u8 csr; sh_wdt_stop() local
181 u8 csr; sh_wdt_ping() local
[all...]
/kernel/linux/linux-6.6/drivers/watchdog/
H A Dshwdt.c85 u8 csr; in sh_wdt_start() local
95 csr = sh_wdt_read_csr(); in sh_wdt_start()
96 csr |= WTCSR_WT | clock_division_ratio; in sh_wdt_start()
97 sh_wdt_write_csr(csr); in sh_wdt_start()
109 csr = sh_wdt_read_csr(); in sh_wdt_start()
110 csr |= WTCSR_TME; in sh_wdt_start()
111 csr &= ~WTCSR_RSTS; in sh_wdt_start()
112 sh_wdt_write_csr(csr); in sh_wdt_start()
115 csr = sh_wdt_read_rstcsr(); in sh_wdt_start()
116 csr in sh_wdt_start()
128 u8 csr; sh_wdt_stop() local
181 u8 csr; sh_wdt_ping() local
[all...]
/kernel/linux/linux-5.10/drivers/scsi/
H A Dsun3_scsi.c73 unsigned short csr; /* control/status reg */ member
117 /* bits in csr reg */
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr in sun3scsi_dma_setup()
348 unsigned short csr; sun3scsi_dma_start() local
[all...]
/kernel/linux/linux-6.6/drivers/scsi/
H A Dsun3_scsi.c73 unsigned short csr; /* control/status reg */ member
117 /* bits in csr reg */
196 unsigned short csr = dregs->csr; in scsi_sun3_intr() local
200 dregs->csr &= ~CSR_DMA_ENABLE; in scsi_sun3_intr()
203 if(csr & ~CSR_GOOD) { in scsi_sun3_intr()
204 if (csr & CSR_DMA_BUSERR) in scsi_sun3_intr()
206 if (csr & CSR_DMA_CONFLICT) in scsi_sun3_intr()
211 if(csr & (CSR_SDB_INT | CSR_DMA_INT)) { in scsi_sun3_intr()
242 dregs->csr in sun3scsi_dma_setup()
348 unsigned short csr; sun3scsi_dma_start() local
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/kernel/linux/linux-5.10/arch/sh/kernel/cpu/
H A Dadc.c16 unsigned char csr; in adc_single() local
22 csr = __raw_readb(ADCSR); in adc_single()
23 csr = channel | ADCSR_ADST | ADCSR_CKS; in adc_single()
24 __raw_writeb(csr, ADCSR); in adc_single()
27 csr = __raw_readb(ADCSR); in adc_single()
28 } while ((csr & ADCSR_ADF) == 0); in adc_single()
30 csr &= ~(ADCSR_ADF | ADCSR_ADST); in adc_single()
31 __raw_writeb(csr, ADCSR); in adc_single()

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