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Searched refs:cntr_idx (Results 1 - 16 of 16) sorted by relevance

/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-etm3x-sysfs.c580 val = config->cntr_idx; in cntr_idx_show()
604 config->cntr_idx = val; in cntr_idx_store()
609 static DEVICE_ATTR_RW(cntr_idx);
619 val = config->cntr_rld_val[config->cntr_idx]; in cntr_rld_val_show()
639 config->cntr_rld_val[config->cntr_idx] = val; in cntr_rld_val_store()
654 val = config->cntr_event[config->cntr_idx]; in cntr_event_show()
674 config->cntr_event[config->cntr_idx] = val & ETM_EVENT_MASK; in cntr_event_store()
689 val = config->cntr_rld_event[config->cntr_idx]; in cntr_rld_event_show()
709 config->cntr_rld_event[config->cntr_idx] = val & ETM_EVENT_MASK; in cntr_rld_event_store()
755 config->cntr_val[config->cntr_idx] in cntr_val_store()
[all...]
H A Dcoresight-etm4x-sysfs.c231 config->cntr_idx = 0x0; in reset_store()
1508 val = config->cntr_idx; in cntr_idx_show()
1530 config->cntr_idx = val; in cntr_idx_store()
1534 static DEVICE_ATTR_RW(cntr_idx);
1546 idx = config->cntr_idx; in cntrldvr_show()
1567 idx = config->cntr_idx; in cntrldvr_store()
1584 idx = config->cntr_idx; in cntr_val_show()
1605 idx = config->cntr_idx; in cntr_val_store()
1622 idx = config->cntr_idx; in cntr_ctrl_show()
1641 idx = config->cntr_idx; in cntr_ctrl_store()
[all...]
H A Dcoresight-etm.h157 * @cntr_idx: index for the counter register selection.
189 u8 cntr_idx; member
H A Dcoresight-etm4x.h230 * @cntr_idx: Counter index seletor.
274 u8 cntr_idx; member
/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-etm3x-sysfs.c581 val = config->cntr_idx; in cntr_idx_show()
605 config->cntr_idx = val; in cntr_idx_store()
610 static DEVICE_ATTR_RW(cntr_idx);
620 val = config->cntr_rld_val[config->cntr_idx]; in cntr_rld_val_show()
640 config->cntr_rld_val[config->cntr_idx] = val; in cntr_rld_val_store()
655 val = config->cntr_event[config->cntr_idx]; in cntr_event_show()
675 config->cntr_event[config->cntr_idx] = val & ETM_EVENT_MASK; in cntr_event_store()
690 val = config->cntr_rld_event[config->cntr_idx]; in cntr_rld_event_show()
710 config->cntr_rld_event[config->cntr_idx] = val & ETM_EVENT_MASK; in cntr_rld_event_store()
756 config->cntr_val[config->cntr_idx] in cntr_val_store()
[all...]
H A Dcoresight-etm4x-sysfs.c232 config->cntr_idx = 0x0; in reset_store()
1517 val = config->cntr_idx; in cntr_idx_show()
1539 config->cntr_idx = val; in cntr_idx_store()
1543 static DEVICE_ATTR_RW(cntr_idx);
1555 idx = config->cntr_idx; in cntrldvr_show()
1576 idx = config->cntr_idx; in cntrldvr_store()
1593 idx = config->cntr_idx; in cntr_val_show()
1614 idx = config->cntr_idx; in cntr_val_store()
1631 idx = config->cntr_idx; in cntr_ctrl_show()
1650 idx = config->cntr_idx; in cntr_ctrl_store()
[all...]
H A Dcoresight-etm.h157 * @cntr_idx: index for the counter register selection.
189 u8 cntr_idx; member
H A Dcoresight-etm4x.h818 * @cntr_idx: Counter index seletor.
862 u8 cntr_idx; member
/kernel/linux/linux-6.6/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c71 static u32 hisi_ddrc_pmu_v1_get_counter_offset(int cntr_idx) in hisi_ddrc_pmu_v1_get_counter_offset() argument
73 return ddrc_reg_off[cntr_idx]; in hisi_ddrc_pmu_v1_get_counter_offset()
76 static u32 hisi_ddrc_pmu_v2_get_counter_offset(int cntr_idx) in hisi_ddrc_pmu_v2_get_counter_offset() argument
78 return DDRC_V2_EVENT_CNT + cntr_idx * 8; in hisi_ddrc_pmu_v2_get_counter_offset()
H A Dhisi_uncore_l3c_pmu.c228 static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx) in hisi_l3c_pmu_get_counter_offset() argument
230 return (L3C_CNTR0_LOWER + (cntr_idx * 8)); in hisi_l3c_pmu_get_counter_offset()
H A Dhisi_uncore_hha_pmu.c163 static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx) in hisi_hha_pmu_get_counter_offset() argument
165 return (HHA_CNT0_LOWER + (cntr_idx * 8)); in hisi_hha_pmu_get_counter_offset()
/kernel/linux/linux-5.10/drivers/perf/hisilicon/
H A Dhisi_uncore_ddrc_pmu.c59 static u32 hisi_ddrc_pmu_get_counter_offset(int cntr_idx) in hisi_ddrc_pmu_get_counter_offset() argument
61 return ddrc_reg_off[cntr_idx]; in hisi_ddrc_pmu_get_counter_offset()
H A Dhisi_uncore_hha_pmu.c45 static u32 hisi_hha_pmu_get_counter_offset(int cntr_idx) in hisi_hha_pmu_get_counter_offset() argument
47 return (HHA_CNT0_LOWER + (cntr_idx * 8)); in hisi_hha_pmu_get_counter_offset()
H A Dhisi_uncore_l3c_pmu.c44 static u32 hisi_l3c_pmu_get_counter_offset(int cntr_idx) in hisi_l3c_pmu_get_counter_offset() argument
46 return (L3C_CNTR0_LOWER + (cntr_idx * 8)); in hisi_l3c_pmu_get_counter_offset()
/kernel/linux/linux-5.10/arch/x86/events/intel/
H A Dp4.c1215 int cntr_idx, escr_idx; in p4_pmu_schedule_events() local
1243 cntr_idx = hwc->idx; in p4_pmu_schedule_events()
1249 cntr_idx = p4_next_cntr(thread, used_mask, bind); in p4_pmu_schedule_events()
1250 if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) { in p4_pmu_schedule_events()
1281 assign[i] = cntr_idx; in p4_pmu_schedule_events()
1283 set_bit(cntr_idx, used_mask); in p4_pmu_schedule_events()
/kernel/linux/linux-6.6/arch/x86/events/intel/
H A Dp4.c1248 int cntr_idx, escr_idx; in p4_pmu_schedule_events() local
1276 cntr_idx = hwc->idx; in p4_pmu_schedule_events()
1282 cntr_idx = p4_next_cntr(thread, used_mask, bind); in p4_pmu_schedule_events()
1283 if (cntr_idx == -1 || test_bit(escr_idx, escr_mask)) { in p4_pmu_schedule_events()
1314 assign[i] = cntr_idx; in p4_pmu_schedule_events()
1316 set_bit(cntr_idx, used_mask); in p4_pmu_schedule_events()

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