Searched refs:cfgcr0 (Results 1 - 8 of 8) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.c | 2325 val = pll->state.hw_state.cfgcr0; in cnl_ddi_pll_enable()
2333 if (pll->state.hw_state.cfgcr0 & DPLL_CFGCR0_HDMI_MODE) { in cnl_ddi_pll_enable()
2443 hw_state->cfgcr0 = val; in cnl_ddi_pll_get_hw_state()
2600 u32 cfgcr0, cfgcr1; in cnl_ddi_hdmi_pll_dividers() local
2603 cfgcr0 = DPLL_CFGCR0_HDMI_MODE; in cnl_ddi_hdmi_pll_dividers()
2608 cfgcr0 |= DPLL_CFGCR0_DCO_FRACTION(wrpll_params.dco_fraction) | in cnl_ddi_hdmi_pll_dividers()
2620 crtc_state->dpll_hw_state.cfgcr0 = cfgcr0; in cnl_ddi_hdmi_pll_dividers()
2680 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in __cnl_ddi_wrpll_get_freq()
2683 dco_fraction = (pll_state->cfgcr0 in __cnl_ddi_wrpll_get_freq()
2706 u32 cfgcr0; cnl_ddi_dp_set_dpll_hw_state() local
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| H A D | intel_dpll_mgr.h | 191 u32 cfgcr0; member
199 * u32 cfgcr0, cfgcr1;
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| H A D | intel_display_debugfs.c | 942 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
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| H A D | intel_display.c | 13998 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
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| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_dpll_mgr.h | 201 u32 cfgcr0; member
211 * u32 cfgcr0, cfgcr1;
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| H A D | intel_dpll_mgr.c | 2730 dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) * in icl_ddi_combo_pll_get_freq()
2733 dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >> in icl_ddi_combo_pll_get_freq()
2756 pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) | in icl_calc_dpll_state()
3553 hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3556 hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id)); in icl_pll_get_hw_state()
3559 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3564 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3575 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3580 hw_state->cfgcr0 = intel_de_read(dev_priv, in icl_pll_get_hw_state()
3640 intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0); in icl_dpll_write()
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| H A D | intel_display_debugfs.c | 667 seq_printf(m, " cfgcr0: 0x%08x\n", pll->state.hw_state.cfgcr0); in i915_shared_dplls_info()
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| H A D | intel_display.c | 5325 PIPE_CONF_CHECK_X(dpll_hw_state.cfgcr0); in intel_pipe_config_compare()
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