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Help
Searched
refs:cache_addr
(Results
1 - 8
of
8
) sorted by relevance
/kernel/linux/linux-5.10/drivers/net/wireless/intel/iwlwifi/
H
A
D
iwl-eeprom-read.c
354
u16
cache_addr
= 0;
in iwl_read_eeprom()
local
411
e[
cache_addr
/ 2] = eeprom_data;
in iwl_read_eeprom()
412
cache_addr
+= sizeof(u16);
in iwl_read_eeprom()
/kernel/linux/linux-6.6/drivers/net/wireless/intel/iwlwifi/
H
A
D
iwl-eeprom-read.c
296
u16
cache_addr
= 0;
in iwl_read_eeprom()
local
353
e[
cache_addr
/ 2] = eeprom_data;
in iwl_read_eeprom()
354
cache_addr
+= sizeof(u16);
in iwl_read_eeprom()
/kernel/linux/linux-5.10/arch/sh/mm/
H
A
D
cache-sh2a.c
39
static void sh2a_invalidate_line(unsigned long
cache_addr
, unsigned long v)
in sh2a_invalidate_line()
argument
43
__raw_writel((addr & CACHE_PHYSADDR_MASK),
cache_addr
| addr);
in sh2a_invalidate_line()
/kernel/linux/linux-6.6/arch/sh/mm/
H
A
D
cache-sh2a.c
39
static void sh2a_invalidate_line(unsigned long
cache_addr
, unsigned long v)
in sh2a_invalidate_line()
argument
43
__raw_writel((addr & CACHE_PHYSADDR_MASK),
cache_addr
| addr);
in sh2a_invalidate_line()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H
A
D
vcn_v3_0.c
1219
uint64_t
cache_addr
;
in vcn_v3_0_start_sriov()
local
1301
cache_addr
= adev->vcn.inst[i].gpu_addr + offset;
in vcn_v3_0_start_sriov()
1304
lower_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1307
upper_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1315
cache_addr
= adev->vcn.inst[i].gpu_addr + offset +
in vcn_v3_0_start_sriov()
1319
lower_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1322
upper_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H
A
D
vcn_v4_0.c
1217
uint64_t
cache_addr
;
in vcn_v4_0_start_sriov()
local
1298
cache_addr
= adev->vcn.inst[i].gpu_addr + offset;
in vcn_v4_0_start_sriov()
1301
lower_32_bits(
cache_addr
));
in vcn_v4_0_start_sriov()
1304
upper_32_bits(
cache_addr
));
in vcn_v4_0_start_sriov()
1312
cache_addr
= adev->vcn.inst[i].gpu_addr + offset +
in vcn_v4_0_start_sriov()
1316
lower_32_bits(
cache_addr
));
in vcn_v4_0_start_sriov()
1319
upper_32_bits(
cache_addr
));
in vcn_v4_0_start_sriov()
H
A
D
vcn_v4_0_3.c
852
uint64_t
cache_addr
;
in vcn_v4_0_3_start_sriov()
local
928
cache_addr
= adev->vcn.inst[vcn_inst].gpu_addr + offset;
in vcn_v4_0_3_start_sriov()
930
regUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW), lower_32_bits(
cache_addr
));
in vcn_v4_0_3_start_sriov()
932
regUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH), upper_32_bits(
cache_addr
));
in vcn_v4_0_3_start_sriov()
938
cache_addr
= adev->vcn.inst[vcn_inst].gpu_addr + offset +
in vcn_v4_0_3_start_sriov()
942
regUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW), lower_32_bits(
cache_addr
));
in vcn_v4_0_3_start_sriov()
945
regUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH), upper_32_bits(
cache_addr
));
in vcn_v4_0_3_start_sriov()
H
A
D
vcn_v3_0.c
1286
uint64_t
cache_addr
;
in vcn_v3_0_start_sriov()
local
1362
cache_addr
= adev->vcn.inst[i].gpu_addr + offset;
in vcn_v3_0_start_sriov()
1365
lower_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1368
upper_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1376
cache_addr
= adev->vcn.inst[i].gpu_addr + offset +
in vcn_v3_0_start_sriov()
1380
lower_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
1383
upper_32_bits(
cache_addr
));
in vcn_v3_0_start_sriov()
Completed in 12 milliseconds