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/kernel/linux/linux-5.10/arch/arm/mm/
H A Dproc-arm940.S51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
184 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
233 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
276 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
279 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
280 mcr p15, 0, r0, c6, c4, 0
281 mcr p15, 0, r0, c6, c5, 0
282 mcr p15, 0, r0, c6, c6,
[all...]
H A Dproc-arm740.S64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
68 mcr p15, 0, r0, c6, c7
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
94 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
H A Dproc-arm946.S58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
233 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
329 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
332 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
333 mcr p15, 0, r0, c6, c4, 0
334 mcr p15, 0, r0, c6, c
[all...]
H A Dpmsa-v7.c38 #define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
39 #define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
40 #define DRSR __ACCESS_CP15(c6, 0, c1, 2)
41 #define IRSR __ACCESS_CP15(c6, 0, c1, 3)
42 #define DRACR __ACCESS_CP15(c6, 0, c1, 4)
43 #define IRACR __ACCESS_CP15(c6, 0, c1, 5)
44 #define RNGNR __ACCESS_CP15(c6, 0, c2, 0)
H A Dcache-v4wt.S71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-arm925.S166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
291 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
333 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
395 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
H A Dproc-arm926.S132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
358 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
H A Dcache-v4wb.S118 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
165 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
192 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dtlb-v6.S46 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
75 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
H A Dpmsa-v8.c21 #define PRSEL __ACCESS_CP15(c6, 0, c2, 1)
22 #define PRBAR __ACCESS_CP15(c6, 0, c3, 0)
23 #define PRLAR __ACCESS_CP15(c6, 0, c3, 1)
/kernel/linux/linux-6.6/arch/arm/mm/
H A Dproc-arm940.S51 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
108 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
184 2: mcr p15, 0, r3, c7, c6, 2 @ flush D entry
233 mcr p15, 0, r3, c7, c6, 2 @ invalidate D entry
276 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
279 mcr p15, 0, r0, c6, c3, 0 @ disable data area 3~7
280 mcr p15, 0, r0, c6, c4, 0
281 mcr p15, 0, r0, c6, c5, 0
282 mcr p15, 0, r0, c6, c6,
[all...]
H A Dproc-arm740.S64 mcr p15, 0, r0, c6, c3 @ disable area 3~7
65 mcr p15, 0, r0, c6, c4
66 mcr p15, 0, r0, c6, c5
67 mcr p15, 0, r0, c6, c6
68 mcr p15, 0, r0, c6, c7
71 mcr p15, 0, r0, c6, c0 @ set area 0, default
81 mcr p15, 0, r0, c6, c1 @ set area 1, RAM
94 2: mcr p15, 0, r0, c6, c2 @ set area 2, ROM/FLASH
H A Dproc-arm946.S58 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
103 mcr p15, 0, ip, c7, c6, 0 @ flush D cache
137 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
140 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
233 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
277 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
329 mcr p15, 0, r0, c7, c6, 0 @ invalidate D cache
332 mcr p15, 0, r0, c6, c3, 0 @ disable memory region 3~7
333 mcr p15, 0, r0, c6, c4, 0
334 mcr p15, 0, r0, c6, c
[all...]
H A Dpmsa-v7.c38 #define DRBAR __ACCESS_CP15(c6, 0, c1, 0)
39 #define IRBAR __ACCESS_CP15(c6, 0, c1, 1)
40 #define DRSR __ACCESS_CP15(c6, 0, c1, 2)
41 #define IRSR __ACCESS_CP15(c6, 0, c1, 3)
42 #define DRACR __ACCESS_CP15(c6, 0, c1, 4)
43 #define IRACR __ACCESS_CP15(c6, 0, c1, 5)
44 #define RNGNR __ACCESS_CP15(c6, 0, c2, 0)
H A Dcache-v4wt.S71 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
89 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
157 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dproc-arm925.S166 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
196 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
199 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
291 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
333 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
395 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
H A Dproc-arm926.S132 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
159 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
162 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
254 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
296 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
358 mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache
H A Dcache-v4wb.S117 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
164 mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
191 1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry
H A Dtlb-v6.S48 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA (was 1)
77 mcr p15, 0, r0, c8, c6, 1 @ TLB invalidate D MVA
H A Dpmsa-v8.c21 #define PRSEL __ACCESS_CP15(c6, 0, c2, 1)
22 #define PRBAR __ACCESS_CP15(c6, 0, c3, 0)
23 #define PRLAR __ACCESS_CP15(c6, 0, c3, 1)
/kernel/linux/linux-5.10/arch/arm/kernel/
H A Dhead-nommu.S218 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
223 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
224 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
225 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
336 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
349 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
350 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
363 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
364 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
387 AR_CLASS(mcr p15, 0, r5, c6, c
[all...]
/kernel/linux/linux-6.6/arch/arm/kernel/
H A Dhead-nommu.S219 mcr p15, 0, \tmp, c6, c2, 0 @ Write RGNR
224 mcr p15, 0, \bar, c6, c1, (0 + \side) @ I/DRBAR
225 mcr p15, 0, \acr, c6, c1, (4 + \side) @ I/DRACR
226 mcr p15, 0, \sr, c6, c1, (2 + \side) @ I/DRSR
337 AR_CLASS(mcr p15, 0, r0, c6, c2, 1) @ PRSEL
350 AR_CLASS(mcr p15, 0, r5, c6, c8, 0) @ PRBAR0
351 AR_CLASS(mcr p15, 0, r6, c6, c8, 1) @ PRLAR0
364 AR_CLASS(mcr p15, 0, r5, c6, c8, 4) @ PRBAR1
365 AR_CLASS(mcr p15, 0, r6, c6, c8, 5) @ PRLAR1
388 AR_CLASS(mcr p15, 0, r5, c6, c
[all...]
/kernel/linux/linux-5.10/arch/arm/include/asm/hardware/
H A Dcp14.h48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
63 #define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
79 #define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
95 #define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
111 #define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
128 #define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
168 #define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
184 #define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
200 #define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6,
[all...]
/kernel/linux/linux-6.6/arch/arm/include/asm/hardware/
H A Dcp14.h48 #define RCP14_DBGWFAR() MRC14(0, c0, c6, 0)
63 #define RCP14_DBGBVR6() MRC14(0, c0, c6, 4)
79 #define RCP14_DBGBCR6() MRC14(0, c0, c6, 5)
95 #define RCP14_DBGWVR6() MRC14(0, c0, c6, 6)
111 #define RCP14_DBGWCR6() MRC14(0, c0, c6, 7)
128 #define RCP14_DBGBXVR6() MRC14(0, c1, c6, 1)
153 #define WCP14_DBGWFAR(val) MCR14(val, 0, c0, c6, 0)
168 #define WCP14_DBGBVR6(val) MCR14(val, 0, c0, c6, 4)
184 #define WCP14_DBGBCR6(val) MCR14(val, 0, c0, c6, 5)
200 #define WCP14_DBGWVR6(val) MCR14(val, 0, c0, c6,
[all...]
/kernel/liteos_a/arch/arm/arm/include/
H A Dlos_hw_cpu.h115 * Memory system fault registers (c5 & c6)
119 #define DFAR CP15_REG(c6, 0, c0, 0) /* Data Fault Address Register */
120 #define IFAR CP15_REG(c6, 0, c0, 2) /* Instruction Fault Address Register */

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