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Searched refs:TRCVIPCSSCTLR (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-cfg.c53 if (((offset >= TRCEVENTCTL0R) && (offset <= TRCVIPCSSCTLR)) || in etm4_cfg_map_reg_offset()
67 CHECKREG(TRCVIPCSSCTLR, vipcssctlr); in etm4_cfg_map_reg_offset()
H A Dcoresight-etm4x.h45 #define TRCVIPCSSCTLR 0x08C macro
297 CASE_##op((val), TRCVIPCSSCTLR) \
H A Dcoresight-etm4x-core.c454 etm4x_relaxed_write32(csa, config->vipcssctlr, TRCVIPCSSCTLR); in etm4_enable_hw()
1703 state->trcvipcssctlr = etm4x_read32(csa, TRCVIPCSSCTLR); in __etm4_cpu_save()
1834 etm4x_relaxed_write32(csa, state->trcvipcssctlr, TRCVIPCSSCTLR); in __etm4_cpu_restore()
/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h42 #define TRCVIPCSSCTLR 0x08C macro
H A Dcoresight-etm4x-core.c147 drvdata->base + TRCVIPCSSCTLR); in etm4_enable_hw()
1204 state->trcvipcssctlr = readl(drvdata->base + TRCVIPCSSCTLR); in etm4_cpu_save()
1315 writel_relaxed(state->trcvipcssctlr, drvdata->base + TRCVIPCSSCTLR); in etm4_cpu_restore()

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