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Searched refs:TRCCIDCCTLR1 (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-etm4x-cfg.c72 CHECKREG(TRCCIDCCTLR1, ctxid_mask1); in etm4_cfg_map_reg_offset()
H A Dcoresight-etm4x.h100 #define TRCCIDCCTLR1 0x684 macro
458 CASE_##op((val), TRCCIDCCTLR1) \
H A Dcoresight-etm4x-core.c492 etm4x_relaxed_write32(csa, config->ctxid_mask1, TRCCIDCCTLR1); in etm4_enable_hw()
1753 state->trccidcctlr1 = etm4x_read32(csa, TRCCIDCCTLR1); in __etm4_cpu_save()
1877 etm4x_relaxed_write32(csa, state->trccidcctlr1, TRCCIDCCTLR1); in __etm4_cpu_restore()
/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h91 #define TRCCIDCCTLR1 0x684 macro
H A Dcoresight-etm4x-core.c193 writel_relaxed(config->ctxid_mask1, drvdata->base + TRCCIDCCTLR1); in etm4_enable_hw()
1251 state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); in etm4_cpu_save()
1367 writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1); in etm4_cpu_restore()

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