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Searched refs:TRCACATRn (Results 1 - 5 of 5) sorted by relevance

/kernel/linux/linux-6.6/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h92 #define TRCACATRn(n) (0x480 + (n * 8)) macro
409 CASE_##op((val), TRCACATRn(0)) \
410 CASE_##op((val), TRCACATRn(1)) \
411 CASE_##op((val), TRCACATRn(2)) \
412 CASE_##op((val), TRCACATRn(3)) \
413 CASE_##op((val), TRCACATRn(4)) \
414 CASE_##op((val), TRCACATRn(5)) \
415 CASE_##op((val), TRCACATRn(6)) \
416 CASE_##op((val), TRCACATRn(7)) \
417 CASE_##op((val), TRCACATRn(
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H A Dcoresight-etm4x-cfg.c109 (offset <= TRCACATRn((ETM_MAX_SINGLE_ADDR_CMP - 1)))) { in etm4_cfg_map_reg_offset()
115 CHECKREGIDX(TRCACATRn(0), addr_acc, idx, off_mask); in etm4_cfg_map_reg_offset()
H A Dcoresight-etm4x-core.c486 etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i)); in etm4_enable_hw()
1735 state->trcacatr[i] = etm4x_read64(csa, TRCACATRn(i)); in __etm4_cpu_save()
1866 etm4x_relaxed_write64(csa, state->trcacatr[i], TRCACATRn(i)); in __etm4_cpu_restore()
/kernel/linux/linux-5.10/drivers/hwtracing/coresight/
H A Dcoresight-etm4x.h85 #define TRCACATRn(n) (0x480 + (n * 8)) macro
184 /* secure state access levels - TRCACATRn */
189 /* non-secure state access levels - TRCACATRn */
195 /* access level control in TRCVICTLR - same bits as TRCACATRn but shifted */
H A Dcoresight-etm4x-core.c186 drvdata->base + TRCACATRn(i)); in etm4_enable_hw()
806 * bits in vinst_ctrl, same bit pattern as TRCACATRn values returned by in etm4_set_victlr_access()
1233 state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i)); in etm4_cpu_save()
1354 drvdata->base + TRCACATRn(i)); in etm4_cpu_restore()

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