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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 - 25 of 28) sorted by relevance

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/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dcik.c7062 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7064 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7065 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7066 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7067 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7068 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7069 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7074 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7082 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
[all...]
H A Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Devergreen.c4525 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4529 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4533 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4539 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
H A Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dsi.c6087 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6091 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6095 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
H A Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600.c3825 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dcik.c7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
[all...]
H A Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Devergreen.c4527 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4531 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4535 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4541 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
H A Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dsi.c6082 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6086 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6090 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
H A Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v11_0.c5742 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
5750 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_gfx_eop_interrupt_state()
5799 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
5807 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dsid.h1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dgfx_v9_4_3.c2743 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
2749 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c5718 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5765 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5771 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c8789 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
8795 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
8842 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
8848 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dgfx_v9_0.c5651 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5698 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5704 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c8236 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
8242 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
8289 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
8295 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()

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