SMU_SCLK_DPM_STATE_0_CNTL_1 (reference) in projects: kernel - OpenGrok search results

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Searched refs:SMU_SCLK_DPM_STATE_0_CNTL_1 (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	trinityd.h	`47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 macro`
H A D	trinity_dpm.c	618 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers() 621 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers() 630 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers() 633 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers() 684 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_display_wm() 687 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_display_wm() 696 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_vce_wm() 699 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_vce_wm()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	trinityd.h	`47 #define SMU_SCLK_DPM_STATE_0_CNTL_1 0x1f004 macro`
H A D	trinity_dpm.c	574 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ds_dividers() 577 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ds_dividers() 586 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_ss_dividers() 589 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_ss_dividers() 640 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_display_wm() 643 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_display_wm() 652 value = RREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix); in trinity_set_vce_wm() 655 WREG32_SMC(SMU_SCLK_DPM_STATE_0_CNTL_1 + ix, value); in trinity_set_vce_wm()

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