Searched refs:SEC_CONTROL_REG (Results 1 - 2 of 2) sorted by relevance
| /kernel/linux/linux-5.10/drivers/crypto/hisilicon/sec2/ |
| H A D | sec_main.c | 61 #define SEC_CONTROL_REG 0x0200 macro
258 SEC_ACC_COMMON_REG_OFF + SEC_CONTROL_REG); in sec_get_endian()
279 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
281 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
293 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
295 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
320 reg = readl_relaxed(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
322 writel_relaxed(reg, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_engine_init()
382 val = readl(SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
398 writel(val, SEC_ADDR(qm, SEC_CONTROL_REG)); in sec_hw_error_enable()
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| /kernel/linux/linux-6.6/drivers/crypto/hisilicon/sec2/ |
| H A D | sec_main.c | 54 #define SEC_CONTROL_REG 0x301200 macro
428 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
436 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_set_endian()
520 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
522 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_enable_clock_gate()
538 val = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
540 writel_relaxed(val, qm->io_base + SEC_CONTROL_REG); in sec_disable_clock_gate()
561 reg = readl_relaxed(qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
563 writel_relaxed(reg, qm->io_base + SEC_CONTROL_REG); in sec_engine_init()
638 val1 = readl(qm->io_base + SEC_CONTROL_REG); in sec_master_ooo_ctrl()
[all...] |
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