| /kernel/linux/linux-5.10/drivers/mmc/host/ |
| H A D | sdhci-pci-gli.c | 214 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
216 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
234 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
236 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
280 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_execute_tuning_9750()
640 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
651 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
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| H A D | sdhci-xenon.c | 200 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
218 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
286 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_ios()
288 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); in xenon_set_ios()
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| H A D | sdhci-of-dwcmshc.c | 82 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
100 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
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| H A D | sdhci-sprd.c | 52 /* SDHCI_HOST_CONTROL2 */
319 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
351 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
536 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
539 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
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| H A D | sdhci-brcmstb.c | 102 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
121 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
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| H A D | sdhci.c | 99 sdhci_readw(host, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs()
131 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
136 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
304 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
306 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
1408 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_auto_cmd_select()
1413 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_auto_cmd_select()
2241 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_uhs_signaling()
2258 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_uhs_signaling()
2392 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_ios()
[all...] |
| H A D | sdhci-acpi.c | 594 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
596 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
598 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
600 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
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| H A D | sdhci-st.c | 261 u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
304 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
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| H A D | sdhci-pxav3.c | 250 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
294 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
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| H A D | sdhci-msm.c | 1307 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1367 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1525 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 in sdhci_msm_check_power_status()
1941 case SDHCI_HOST_CONTROL2: in __sdhci_msm_check_write()
2078 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2100 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2107 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
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| H A D | sdhci-pci-core.c | 1692 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1694 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1696 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1698 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
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| H A D | sdhci.h | 181 #define SDHCI_HOST_CONTROL2 0x3E macro
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| H A D | sdhci-pci-o2micro.c | 207 u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_o2_execute_tuning()
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| /kernel/linux/linux-6.6/drivers/mmc/host/ |
| H A D | sdhci-xenon.c | 201 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
219 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in xenon_set_uhs_signaling()
297 reg = sdhci_readw(host, SDHCI_HOST_CONTROL2); in xenon_set_ios()
299 sdhci_writew(host, reg, SDHCI_HOST_CONTROL2); in xenon_set_ios()
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| H A D | sdhci.c | 98 sdhci_readw(host, SDHCI_HOST_CONTROL2)); in sdhci_dumpregs()
130 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
135 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_do_enable_v4_mode()
343 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
345 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_config_dma()
1430 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_auto_cmd_select()
1435 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in sdhci_auto_cmd_select()
2266 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_uhs_signaling()
2283 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_uhs_signaling()
2430 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_ios()
[all...] |
| H A D | sdhci-acpi.c | 550 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
552 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
554 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_set_ios()
556 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_set_ios()
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| H A D | sdhci-sprd.c | 57 /* SDHCI_HOST_CONTROL2 */
343 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
375 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_set_uhs_signaling()
560 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
563 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_sprd_hs400_enhanced_strobe()
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| H A D | sdhci-pci-gli.c | 331 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
333 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
351 ctrl2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in gli_set_9750()
353 sdhci_writew(host, ctrl2, SDHCI_HOST_CONTROL2); in gli_set_9750()
397 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in __sdhci_execute_tuning_9750()
1223 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
1234 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_set_gl9763e_signaling()
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| H A D | sdhci-brcmstb.c | 104 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
123 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_brcmstb_set_uhs_signaling()
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| H A D | sdhci-st.c | 261 u16 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
304 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_st_set_uhs_signaling()
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| H A D | sdhci-pxav3.c | 248 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
292 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in pxav3_set_uhs_signaling()
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| H A D | sdhci-of-dwcmshc.c | 167 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
192 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in dwcmshc_set_uhs_signaling()
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| H A D | sdhci-msm.c | 1327 ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1387 sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); in sdhci_msm_set_uhs_signaling()
1545 * SDHCI_HOST_CONTROL2 register. The reset state of that bit is 0 in sdhci_msm_check_power_status()
2080 case SDHCI_HOST_CONTROL2: in __sdhci_msm_check_write()
2209 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2231 sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
2238 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); in sdhci_msm_start_signal_voltage_switch()
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| H A D | sdhci-pci-core.c | 1637 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1639 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1641 val = sdhci_readw(host, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
1643 sdhci_writew(host, val, SDHCI_HOST_CONTROL2); in amd_tuning_reset()
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| H A D | sdhci.h | 188 #define SDHCI_HOST_CONTROL2 0x3E macro
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