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Help
Searched
refs:SARL
(Results
1 - 11
of
11
) sorted by relevance
/kernel/linux/linux-5.10/drivers/clk/mvebu/
H
A
D
armada-xp.c
26
#define
SARL
0 /* Low part [0:31] */
macro
73
cpu_freq_select = ((readl(sar +
SARL
) >> SARL_AXP_PCLK_FREQ_OPT) &
in axp_get_cpu_freq()
126
u32 opt = ((readl(sar +
SARL
) >> SARL_AXP_FAB_FREQ_OPT) &
in axp_get_clk_ratio()
H
A
D
armada-39x.c
21
*
SARL
[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
23
*
SARL
[15] : TCLK frequency
32
#define
SARL
0
macro
49
tclk_freq_select = ((readl(sar +
SARL
) >> SARL_A390_TCLK_FREQ_OPT) &
in armada_39x_get_tclk_freq()
72
cpu_freq_select = ((readl(sar +
SARL
) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
in armada_39x_get_cpu_freq()
H
A
D
armada-370.c
23
#define
SARL
0 /* Low part [0:31] */
macro
/kernel/linux/linux-6.6/drivers/clk/mvebu/
H
A
D
armada-xp.c
26
#define
SARL
0 /* Low part [0:31] */
macro
73
cpu_freq_select = ((readl(sar +
SARL
) >> SARL_AXP_PCLK_FREQ_OPT) &
in axp_get_cpu_freq()
126
u32 opt = ((readl(sar +
SARL
) >> SARL_AXP_FAB_FREQ_OPT) &
in axp_get_clk_ratio()
H
A
D
armada-39x.c
21
*
SARL
[14:10] : Ratios between CPU, NBCLK, HCLK and DCLK.
23
*
SARL
[15] : TCLK frequency
32
#define
SARL
0
macro
49
tclk_freq_select = ((readl(sar +
SARL
) >> SARL_A390_TCLK_FREQ_OPT) &
in armada_39x_get_tclk_freq()
72
cpu_freq_select = ((readl(sar +
SARL
) >> SARL_A390_CPU_DDR_L2_FREQ_OPT) &
in armada_39x_get_cpu_freq()
H
A
D
armada-370.c
23
#define
SARL
0 /* Low part [0:31] */
macro
/kernel/linux/linux-5.10/drivers/net/wan/
H
A
D
hd64570.h
116
#define
SARL
0x04 /* TX Source Address L (single block) */
macro
H
A
D
hd64572.h
147
#define
SARL
0x80 /* Source Addr Register L (single-block, TX only) */
macro
/kernel/linux/linux-6.6/drivers/net/wan/
H
A
D
hd64570.h
116
#define
SARL
0x04 /* TX Source Address L (single block) */
macro
H
A
D
hd64572.h
147
#define
SARL
0x80 /* Source Addr Register L (single-block, TX only) */
macro
/kernel/linux/linux-5.10/drivers/tty/
H
A
D
synclinkmp.c
358
#define
SARL
0x84
macro
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