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Searched refs:RLC_LB_CNTL (Results 1 - 14 of 14) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c1835 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_0_init_lbpw()
1836 * but used for RLC_LB_CNTL configuration */ in gfx_v9_0_init_lbpw()
1838 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_0_init_lbpw()
1839 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_0_init_lbpw()
1884 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_4_init_lbpw()
1885 * but used for RLC_LB_CNTL configuration */ in gfx_v9_4_init_lbpw()
1887 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_4_init_lbpw()
1888 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_4_init_lbpw()
1897 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_lbpw()
H A Dsid.h1332 #define RLC_LB_CNTL 0x30C3 macro
H A Dgfx_v6_0.c2427 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/amdgpu/
H A Dgfx_v9_0.c1560 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_0_init_lbpw()
1561 * but used for RLC_LB_CNTL configuration */ in gfx_v9_0_init_lbpw()
1563 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_0_init_lbpw()
1564 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_0_init_lbpw()
1609 /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved, in gfx_v9_4_init_lbpw()
1610 * but used for RLC_LB_CNTL configuration */ in gfx_v9_4_init_lbpw()
1612 data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09); in gfx_v9_4_init_lbpw()
1613 data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000); in gfx_v9_4_init_lbpw()
1622 WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v9_0_enable_lbpw()
H A Dsid.h1332 #define RLC_LB_CNTL 0x30C3 macro
H A Dgfx_v6_0.c2391 WREG32_FIELD(RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0); in gfx_v6_0_enable_lbpw()
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A Dcikd.h1403 #define RLC_LB_CNTL 0xC364 macro
H A Dsid.h1304 #define RLC_LB_CNTL 0xC30C macro
H A Dsi.c5856 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5861 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5886 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
H A Dcik.c5784 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
5789 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5945 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A Dcikd.h1403 #define RLC_LB_CNTL 0xC364 macro
H A Dsid.h1304 #define RLC_LB_CNTL 0xC30C macro
H A Dsi.c5851 tmp = RREG32(RLC_LB_CNTL); in si_enable_lbpw()
5856 WREG32(RLC_LB_CNTL, tmp); in si_enable_lbpw()
5881 WREG32(RLC_LB_CNTL, 0); in si_rlc_resume()
H A Dcik.c5773 tmp = RREG32(RLC_LB_CNTL); in cik_enable_lbpw()
5778 WREG32(RLC_LB_CNTL, tmp); in cik_enable_lbpw()
5934 WREG32(RLC_LB_CNTL, 0x80000004); in cik_rlc_resume()

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