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Searched refs:REG_SIZE (Results 1 - 25 of 46) sorted by relevance

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/kernel/linux/linux-6.6/drivers/irqchip/
H A Dqcom-irq-combiner.c24 #define REG_SIZE 32 macro
41 return reg * REG_SIZE + bit; in irq_nr()
82 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_mask_irq()
84 clear_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_mask_irq()
90 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_unmask_irq()
92 set_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_unmask_irq()
186 (reg->bit_width > REG_SIZE)) { in get_registers_cb()
192 vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE); in get_registers_cb()
/kernel/linux/linux-5.10/drivers/irqchip/
H A Dqcom-irq-combiner.c24 #define REG_SIZE 32 macro
41 return reg * REG_SIZE + bit; in irq_nr()
86 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_mask_irq()
88 clear_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_mask_irq()
94 struct combiner_reg *reg = combiner->regs + data->hwirq / REG_SIZE; in combiner_irq_chip_unmask_irq()
96 set_bit(data->hwirq % REG_SIZE, &reg->enabled); in combiner_irq_chip_unmask_irq()
190 (reg->bit_width > REG_SIZE)) { in get_registers_cb()
196 vaddr = devm_ioremap(ctx->dev, reg->address, REG_SIZE); in get_registers_cb()
/kernel/linux/linux-6.6/sound/soc/tegra/
H A Dtegra210_mvc.h92 #define REG_SIZE 4 macro
94 #define TEGRA210_MVC_REG_OFFSET(reg, i) (reg + (REG_SIZE * i))
96 #define TEGRA210_MVC_GET_CHAN(reg, base) (((reg) - (base)) / REG_SIZE)
/kernel/linux/linux-5.10/drivers/staging/kpc2000/
H A Dkpc2000_i2c.c45 #define REG_SIZE 8 macro
48 #define SMBHSTSTS(p) ((0 * REG_SIZE) + (p)->smba)
49 #define SMBHSTCNT(p) ((2 * REG_SIZE) + (p)->smba)
50 #define SMBHSTCMD(p) ((3 * REG_SIZE) + (p)->smba)
51 #define SMBHSTADD(p) ((4 * REG_SIZE) + (p)->smba)
52 #define SMBHSTDAT0(p) ((5 * REG_SIZE) + (p)->smba)
53 #define SMBHSTDAT1(p) ((6 * REG_SIZE) + (p)->smba)
54 #define SMBBLKDAT(p) ((7 * REG_SIZE) + (p)->smba)
55 #define SMBPEC(p) ((8 * REG_SIZE) + (p)->smba) /* ICH3 and later */
56 #define SMBAUXSTS(p) ((12 * REG_SIZE)
[all...]
/kernel/linux/linux-5.10/drivers/hwmon/
H A Dultra45_env.c37 #define REG_SIZE 0x42UL macro
264 p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747"); in env_probe()
288 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_probe()
300 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_remove()
/kernel/linux/linux-6.6/drivers/hwmon/
H A Dultra45_env.c38 #define REG_SIZE 0x42UL macro
265 p->regs = of_ioremap(&op->resource[0], 0, REG_SIZE, "pic16f747"); in env_probe()
289 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_probe()
301 of_iounmap(&op->resource[0], p->regs, REG_SIZE); in env_remove()
/kernel/linux/linux-6.6/drivers/pinctrl/qcom/
H A Dpinctrl-ipq5332.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-ipq5018.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-ipq9574.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-ipq6018.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-ipq8074.c12 #define REG_SIZE 0x1000 macro
31 .ctl_reg = REG_SIZE * id, \
32 .io_reg = 0x4 + REG_SIZE * id, \
33 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
34 .intr_status_reg = 0xc + REG_SIZE * id, \
35 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-msm8909.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdx75.c12 #define REG_SIZE 0x1000 macro
18 .ctl_reg = REG_BASE + REG_SIZE * id, \
19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
22 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdx65.c13 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_BASE + REG_SIZE * id, \
33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdx55.c12 #define REG_SIZE 0x1000 macro
32 .ctl_reg = REG_SIZE * id, \
33 .io_reg = 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
35 .intr_status_reg = 0xc + REG_SIZE * id, \
36 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdm660.c25 #define REG_SIZE 0x1000 macro
45 .ctl_reg = REG_SIZE * id, \
46 .io_reg = 0x4 + REG_SIZE * id, \
47 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
48 .intr_status_reg = 0xc + REG_SIZE * id, \
49 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdm670.c17 #define REG_SIZE 0x1000 macro
36 .ctl_reg = base + REG_SIZE * id, \
37 .io_reg = base + 0x4 + REG_SIZE * id, \
38 .intr_cfg_reg = base + 0x8 + REG_SIZE * id, \
39 .intr_status_reg = base + 0xc + REG_SIZE * id, \
40 .intr_target_reg = base + 0x8 + REG_SIZE * id, \
H A Dpinctrl-qdu1000.c14 #define REG_SIZE 0x1000 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
H A Dpinctrl-msm8976.c15 #define REG_SIZE 0x1000 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
/kernel/linux/linux-6.6/arch/parisc/net/
H A Dbpf_jit_comp32.c209 emit(hppa_ldw(-REG_SIZE * (8 + (i-3)), HPPA_REG_SP, HPPA_R(i)), ctx); in __build_epilogue()
228 emit(hppa_ldw(REG_SIZE * hi(reg) - offset_sp, HPPA_REG_SP, hi(tmp)), ctx); in bpf_get_reg64_offset()
229 emit(hppa_ldw(REG_SIZE * lo(reg) - offset_sp, HPPA_REG_SP, lo(tmp)), ctx); in bpf_get_reg64_offset()
251 emit(hppa_ldw(REG_SIZE * hi(reg), HPPA_REG_SP, hi(tmp)), ctx); in bpf_get_reg64_ref()
264 emit(hppa_stw(hi(src), REG_SIZE * hi(reg), HPPA_REG_SP), ctx); in bpf_put_reg64()
265 emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx); in bpf_put_reg64()
284 emit(hppa_ldw(REG_SIZE * lo(reg), HPPA_REG_SP, lo(tmp)), ctx); in bpf_get_reg32()
309 emit(hppa_stw(lo(src), REG_SIZE * lo(reg), HPPA_REG_SP), ctx); in bpf_put_reg32()
312 emit(hppa_stw(HPPA_REG_ZERO, REG_SIZE * hi(reg), HPPA_REG_SP), ctx); in bpf_put_reg32()
1487 stack_adjust += NR_SAVED_REGISTERS * REG_SIZE; in bpf_jit_build_prologue()
[all...]
H A Dbpf_jit_comp64.c236 emit(hppa64_ldd_im16(-REG_SIZE * i, HPPA_REG_SP, HPPA_R(i)), ctx); in __build_epilogue()
240 emit(hppa64_ldd_im16(-2*REG_SIZE, HPPA_REG_SP, HPPA_REG_RP), ctx); in __build_epilogue()
243 emit(hppa64_ldd_im5(-REG_SIZE, HPPA_REG_SP, HPPA_REG_SP), ctx); in __build_epilogue()
1152 emit(hppa64_std_im5 (HPPA_REG_R1, -REG_SIZE, HPPA_REG_SP), ctx); in bpf_jit_build_prologue()
1153 emit(hppa64_std_im16(HPPA_REG_RP, -2*REG_SIZE, HPPA_REG_SP), ctx); in bpf_jit_build_prologue()
1159 emit(hppa64_std_im16(HPPA_R(i), -REG_SIZE * i, HPPA_REG_SP), ctx); in bpf_jit_build_prologue()
/kernel/linux/linux-5.10/drivers/pinctrl/qcom/
H A Dpinctrl-ipq6018.c20 #define REG_SIZE 0x1000 macro
39 .ctl_reg = REG_SIZE * id, \
40 .io_reg = 0x4 + REG_SIZE * id, \
41 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
42 .intr_status_reg = 0xc + REG_SIZE * id, \
43 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-ipq8074.c20 #define REG_SIZE 0x1000 macro
39 .ctl_reg = REG_SIZE * id, \
40 .io_reg = 0x4 + REG_SIZE * id, \
41 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
42 .intr_status_reg = 0xc + REG_SIZE * id, \
43 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-sdm660.c26 #define REG_SIZE 0x1000 macro
54 .ctl_reg = REG_SIZE * id, \
55 .io_reg = 0x4 + REG_SIZE * id, \
56 .intr_cfg_reg = 0x8 + REG_SIZE * id, \
57 .intr_status_reg = 0xc + REG_SIZE * id, \
58 .intr_target_reg = 0x8 + REG_SIZE * id, \
H A Dpinctrl-msm8976.c23 #define REG_SIZE 0x1000 macro
42 .ctl_reg = REG_BASE + REG_SIZE * id, \
43 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
44 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
45 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
46 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \

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