| /kernel/linux/linux-6.6/arch/mips/n64/ |
| H A D | init.c | 53 #define REG_BASE ((u32 *) CKSEG1ADDR(0x4400000)) macro
57 __raw_writel(value, REG_BASE + reg); in n64rdp_write_reg()
60 #undef REG_BASE macro
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| /kernel/linux/linux-6.6/drivers/pinctrl/qcom/ |
| H A D | pinctrl-qdu1000.c | 13 #define REG_BASE 0x100000 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
60 .ctl_reg = REG_BASE + ctl, \
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| H A D | pinctrl-sdx75.c | 11 #define REG_BASE 0x100000 macro
18 .ctl_reg = REG_BASE + REG_SIZE * id, \
19 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
20 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
21 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
22 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-sdx65.c | 12 #define REG_BASE 0x0 macro
32 .ctl_reg = REG_BASE + REG_SIZE * id, \
33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-msm8976.c | 14 #define REG_BASE 0x0 macro
34 .ctl_reg = REG_BASE + REG_SIZE * id, \
35 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
36 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
37 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
38 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-sa8775p.c | 13 #define REG_BASE 0x100000 macro
33 .ctl_reg = REG_BASE + REG_SIZE * id, \
34 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
35 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
36 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
37 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-msm8996.c | 12 #define REG_BASE 0x0 macro
32 .ctl_reg = REG_BASE + REG_SIZE * id, \
33 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
34 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
35 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
36 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-sm6375.c | 13 #define REG_BASE 0x100000 macro
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| /kernel/linux/linux-5.10/drivers/pinctrl/qcom/ |
| H A D | pinctrl-msm8976.c | 22 #define REG_BASE 0x0 macro
42 .ctl_reg = REG_BASE + REG_SIZE * id, \
43 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
44 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
45 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
46 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
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| H A D | pinctrl-msm8996.c | 20 #define REG_BASE 0x0 macro
40 .ctl_reg = REG_BASE + REG_SIZE * id, \
41 .io_reg = REG_BASE + 0x4 + REG_SIZE * id, \
42 .intr_cfg_reg = REG_BASE + 0x8 + REG_SIZE * id, \
43 .intr_status_reg = REG_BASE + 0xc + REG_SIZE * id, \
44 .intr_target_reg = REG_BASE + 0x8 + REG_SIZE * id, \
|
| /kernel/linux/linux-5.10/drivers/atm/ |
| H A D | midway.h | 23 #define REG_BASE 0x00040000 /* offset of Midway register area */ macro
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| H A D | iphase.h | 633 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE macro
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| H A D | eni.c | 1748 eni_dev->reg = base+REG_BASE; in eni_do_init()
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| H A D | iphase.c | 2387 iadev->reg = base + REG_BASE;
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| /kernel/linux/linux-6.6/drivers/atm/ |
| H A D | midway.h | 23 #define REG_BASE 0x00040000 /* offset of Midway register area */ macro
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| H A D | iphase.h | 632 #define REG_BASE IPHASE5575_BUS_CONTROL_REG_BASE macro
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| H A D | eni.c | 1748 eni_dev->reg = base+REG_BASE; in eni_do_init()
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| H A D | iphase.c | 2388 iadev->reg = base + REG_BASE;
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