Searched refs:REG_A6XX_RSCC_SEQ_MEM_0_DRV0 (Results 1 - 4 of 4) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gmu.c | 542 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); in a6xx_gmu_rpmh_init() 543 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); in a6xx_gmu_rpmh_init() 544 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); in a6xx_gmu_rpmh_init() 545 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); in a6xx_gmu_rpmh_init() 546 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); in a6xx_gmu_rpmh_init() 548 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init() 549 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init() 550 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init() 551 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init() 552 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 in a6xx_gmu_rpmh_init() [all...] |
H A D | a6xx_gmu.xml.h | 468 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 macro
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/kernel/linux/linux-6.6/drivers/gpu/drm/msm/adreno/ |
H A D | a6xx_gmu.c | 556 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xeaaae5a0); in a6xx_gmu_rpmh_init() 557 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xe1a1ebab); in a6xx_gmu_rpmh_init() 558 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e0a581); in a6xx_gmu_rpmh_init() 559 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xecac82e2); in a6xx_gmu_rpmh_init() 560 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020edad); in a6xx_gmu_rpmh_init() 562 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0, 0xa7a506a0); in a6xx_gmu_rpmh_init() 563 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xa1e6a6e7); in a6xx_gmu_rpmh_init() 564 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xa2e081e1); in a6xx_gmu_rpmh_init() 565 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xe9a982e2); in a6xx_gmu_rpmh_init() 566 gmu_write_rscc(gmu, REG_A6XX_RSCC_SEQ_MEM_0_DRV0 in a6xx_gmu_rpmh_init() [all...] |
H A D | a6xx_gmu.xml.h | 474 #define REG_A6XX_RSCC_SEQ_MEM_0_DRV0 0x00000180 macro
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