RADEON_CP_RB_CNTL (reference) in projects: kernel - OpenGrok search results

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Searched refs:RADEON_CP_RB_CNTL (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H A D	r300.c	`431 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset() 432 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in r300_asic_reset() 435 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()`
H A D	rs600.c	`472 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset() 473 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset() 476 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()`
H A D	r100.c	1175 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE); in r100_cp_init() 1181 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE); in r100_cp_init() 1198 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init() 2571 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset() 2572 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in r100_asic_reset() 2575 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset() 4019 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity() 4021 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
H A D	radeon_reg.h	`3297 #define RADEON_CP_RB_CNTL 0x0704 macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H A D	r300.c	`428 tmp = RREG32(RADEON_CP_RB_CNTL); in r300_asic_reset() 429 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in r300_asic_reset() 432 WREG32(RADEON_CP_RB_CNTL, tmp); in r300_asic_reset()`
H A D	rs600.c	`479 tmp = RREG32(RADEON_CP_RB_CNTL); in rs600_asic_reset() 480 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in rs600_asic_reset() 483 WREG32(RADEON_CP_RB_CNTL, tmp); in rs600_asic_reset()`
H A D	r100.c	1183 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_NO_UPDATE); in r100_cp_init() 1189 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA \| RADEON_RB_NO_UPDATE); in r100_cp_init() 1206 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_cp_init() 2579 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_asic_reset() 2580 WREG32(RADEON_CP_RB_CNTL, tmp \| RADEON_RB_RPTR_WR_ENA); in r100_asic_reset() 2583 WREG32(RADEON_CP_RB_CNTL, tmp); in r100_asic_reset() 4007 tmp = RREG32(RADEON_CP_RB_CNTL); in r100_restore_sanity() 4009 WREG32(RADEON_CP_RB_CNTL, 0); in r100_restore_sanity()
H A D	radeon_reg.h	`3297 #define RADEON_CP_RB_CNTL 0x0704 macro`

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