Searched refs:PIPESTAT (Results 1 - 10 of 10) sorted by relevance
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
| H A D | intel_fifo_underrun.c | 46 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
93 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
114 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
|
| H A D | intel_display.c | 19061 PIPESTAT(i)); in intel_display_capture_error_state()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
| H A D | intel_fifo_underrun.c | 50 * is no interrupt (despite that the signalling bit is in the PIPESTAT pipe
97 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
118 i915_reg_t reg = PIPESTAT(pipe); in i9xx_set_fifo_underrun_reporting()
|
| H A D | intel_display_irq.c | 226 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
249 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
403 intel_uncore_write(&dev_priv->uncore, PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
428 * PIPESTAT bits get signalled even when the interrupt is in i9xx_pipestat_irq_ack()
456 reg = PIPESTAT(pipe); in i9xx_pipestat_irq_ack()
|
| /kernel/linux/linux-6.6/drivers/gpu/drm/i915/ |
| H A D | intel_gvt_mmio_table.c | 129 MMIO_D(PIPESTAT(PIPE_A)); in iterate_generic_mmio()
130 MMIO_D(PIPESTAT(PIPE_B)); in iterate_generic_mmio()
131 MMIO_D(PIPESTAT(PIPE_C)); in iterate_generic_mmio()
132 MMIO_D(PIPESTAT(_PIPE_EDP)); in iterate_generic_mmio()
|
| H A D | i915_reg.h | 2646 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
| H A D | i915_debugfs.c | 470 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
563 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
603 I915_READ(PIPESTAT(pipe))); in i915_interrupt_info()
|
| H A D | i915_irq.c | 493 i915_reg_t reg = PIPESTAT(pipe); in i915_enable_pipestat()
516 i915_reg_t reg = PIPESTAT(pipe); in i915_disable_pipestat()
1295 I915_WRITE(PIPESTAT(pipe), in i9xx_pipestat_irq_reset()
1320 * PIPESTAT bits get signalled even when the interrupt is in i9xx_pipestat_irq_ack()
1348 reg = PIPESTAT(pipe); in i9xx_pipestat_irq_ack()
1583 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. in valleyview_irq_handler()
1665 * from PIPESTAT/PORT_HOTPLUG_STAT, hence clear it last. in cherryview_irq_handler()
|
| H A D | i915_reg.h | 6012 #define PIPESTAT(pipe) _MMIO_PIPE2(pipe, _PIPEASTAT) macro
|
| /kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/ |
| H A D | handlers.c | 2045 MMIO_D(PIPESTAT(PIPE_A), D_ALL); in init_generic_mmio_info()
2046 MMIO_D(PIPESTAT(PIPE_B), D_ALL); in init_generic_mmio_info()
2047 MMIO_D(PIPESTAT(PIPE_C), D_ALL); in init_generic_mmio_info()
2048 MMIO_D(PIPESTAT(_PIPE_EDP), D_ALL); in init_generic_mmio_info()
|
Completed in 96 milliseconds