Searched refs:PANEL_POWER_CYCLE_DELAY_MASK (Results 1 - 10 of 10) sorted by relevance
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/display/ |
H A D | intel_pps_regs.h | 76 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) macro
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H A D | intel_lvds.c | 177 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state() 230 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); in intel_lvds_pps_init_hw()
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H A D | intel_pps.c | 1296 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state() 1544 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); in pps_init_registers()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/display/ |
H A D | intel_lvds.c | 171 val = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, val); in intel_lvds_pps_get_hw_state() 220 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(pps->t4, 1000) + 1)); in intel_lvds_pps_init_hw()
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H A D | intel_dp.c | 6969 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; in intel_pps_readout_hw_state() 7173 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); in intel_dp_init_panel_power_sequencer_registers()
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/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/ |
H A D | psb_intel_reg.h | 202 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) macro
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H A D | cdv_intel_dp.c | 2055 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> in cdv_intel_dp_init()
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/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/ |
H A D | psb_intel_reg.h | 202 #define PANEL_POWER_CYCLE_DELAY_MASK (0x1f) macro
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H A D | cdv_intel_dp.c | 2046 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> in cdv_intel_dp_init()
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/kernel/linux/linux-5.10/drivers/gpu/drm/i915/ |
H A D | i915_reg.h | 5059 #define PANEL_POWER_CYCLE_DELAY_MASK REG_GENMASK(4, 0) macro
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