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Help
Searched
refs:NUM_PHASES
(Results
1 - 12
of
12
) sorted by relevance
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn20/
H
A
D
dcn20_dwb_scl.c
32
#define
NUM_PHASES
16
macro
696
for (phase = 0; phase < (
NUM_PHASES
/ 2 + 1); phase++) {
in wbscl_set_scaler_filter()
H
A
D
dcn20_dpp.c
34
#define
NUM_PHASES
64
macro
/kernel/linux/linux-5.10/drivers/mmc/host/
H
A
D
dw_mmc-k3.c
48
#define
NUM_PHASES
(40)
macro
376
for (i = 0; i <
NUM_PHASES
; ++i, ++smpl_phase) {
in dw_mci_hi3660_execute_tuning()
/kernel/linux/linux-6.6/drivers/mmc/host/
H
A
D
dw_mmc-k3.c
48
#define
NUM_PHASES
(40)
macro
376
for (i = 0; i <
NUM_PHASES
; ++i, ++smpl_phase) {
in dw_mci_hi3660_execute_tuning()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn20/
H
A
D
dcn20_dwb_scl.c
32
#define
NUM_PHASES
16
macro
693
for (phase = 0; phase < (
NUM_PHASES
/ 2 + 1); phase++) {
in wbscl_set_scaler_filter()
H
A
D
dcn20_dpp.c
34
#define
NUM_PHASES
64
macro
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/display/dc/dcn10/
H
A
D
dcn10_dpp_dscl.c
35
#define
NUM_PHASES
64
macro
274
for (phase = 0; phase < (
NUM_PHASES
/ 2 + 1); phase++) {
in dpp1_dscl_set_scaler_filter()
H
A
D
dcn10_dpp.c
34
#define
NUM_PHASES
64
macro
H
A
D
dcn10_dpp_cm.c
35
#define
NUM_PHASES
64
macro
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/display/dc/dcn10/
H
A
D
dcn10_dpp_dscl.c
35
#define
NUM_PHASES
64
macro
256
for (phase = 0; phase < (
NUM_PHASES
/ 2 + 1); phase++) {
in dpp1_dscl_set_scaler_filter()
H
A
D
dcn10_dpp.c
34
#define
NUM_PHASES
64
macro
H
A
D
dcn10_dpp_cm.c
35
#define
NUM_PHASES
64
macro
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