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Searched
refs:LinkLevel
(Results
1 - 25
of
28
) sorted by relevance
1
2
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H
A
D
vegam_smumgr.c
581
table->
LinkLevel
[i].PcieGenSpeed =
in vegam_populate_smc_link_level()
583
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in vegam_populate_smc_link_level()
585
table->
LinkLevel
[i].EnabledForActivity = 1;
in vegam_populate_smc_link_level()
586
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in vegam_populate_smc_link_level()
587
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in vegam_populate_smc_link_level()
588
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in vegam_populate_smc_link_level()
2116
table->
LinkLevel
[i - 1].BifSclkDfs =
in vegam_init_smc_table()
H
A
D
fiji_smumgr.c
838
table->
LinkLevel
[i].PcieGenSpeed =
in fiji_populate_smc_link_level()
840
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in fiji_populate_smc_link_level()
842
table->
LinkLevel
[i].EnabledForActivity = 1;
in fiji_populate_smc_link_level()
843
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in fiji_populate_smc_link_level()
844
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in fiji_populate_smc_link_level()
845
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in fiji_populate_smc_link_level()
H
A
D
iceland_smumgr.c
773
table->
LinkLevel
[i].PcieGenSpeed =
in iceland_populate_smc_link_level()
775
table->
LinkLevel
[i].PcieLaneCount =
in iceland_populate_smc_link_level()
777
table->
LinkLevel
[i].EnabledForActivity =
in iceland_populate_smc_link_level()
779
table->
LinkLevel
[i].SPC =
in iceland_populate_smc_link_level()
781
table->
LinkLevel
[i].DownThreshold =
in iceland_populate_smc_link_level()
783
table->
LinkLevel
[i].UpThreshold =
in iceland_populate_smc_link_level()
H
A
D
polaris10_smumgr.c
778
table->
LinkLevel
[i].PcieGenSpeed =
in polaris10_populate_smc_link_level()
780
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in polaris10_populate_smc_link_level()
782
table->
LinkLevel
[i].EnabledForActivity = 1;
in polaris10_populate_smc_link_level()
783
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in polaris10_populate_smc_link_level()
784
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in polaris10_populate_smc_link_level()
785
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in polaris10_populate_smc_link_level()
1996
table->
LinkLevel
[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
in polaris10_init_smc_table()
H
A
D
tonga_smumgr.c
516
table->
LinkLevel
[i].PcieGenSpeed =
in tonga_populate_smc_link_level()
518
table->
LinkLevel
[i].PcieLaneCount =
in tonga_populate_smc_link_level()
520
table->
LinkLevel
[i].EnabledForActivity =
in tonga_populate_smc_link_level()
522
table->
LinkLevel
[i].SPC =
in tonga_populate_smc_link_level()
524
table->
LinkLevel
[i].DownThreshold =
in tonga_populate_smc_link_level()
526
table->
LinkLevel
[i].UpThreshold =
in tonga_populate_smc_link_level()
H
A
D
ci_smumgr.c
1005
table->
LinkLevel
[i].PcieGenSpeed =
in ci_populate_smc_link_level()
1007
table->
LinkLevel
[i].PcieLaneCount =
in ci_populate_smc_link_level()
1009
table->
LinkLevel
[i].EnabledForActivity = 1;
in ci_populate_smc_link_level()
1010
table->
LinkLevel
[i].DownT = PP_HOST_TO_SMC_UL(5);
in ci_populate_smc_link_level()
1011
table->
LinkLevel
[i].UpT = PP_HOST_TO_SMC_UL(30);
in ci_populate_smc_link_level()
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/smumgr/
H
A
D
vegam_smumgr.c
580
table->
LinkLevel
[i].PcieGenSpeed =
in vegam_populate_smc_link_level()
582
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in vegam_populate_smc_link_level()
584
table->
LinkLevel
[i].EnabledForActivity = 1;
in vegam_populate_smc_link_level()
585
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in vegam_populate_smc_link_level()
586
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in vegam_populate_smc_link_level()
587
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in vegam_populate_smc_link_level()
2114
table->
LinkLevel
[i - 1].BifSclkDfs =
in vegam_init_smc_table()
H
A
D
fiji_smumgr.c
837
table->
LinkLevel
[i].PcieGenSpeed =
in fiji_populate_smc_link_level()
839
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in fiji_populate_smc_link_level()
841
table->
LinkLevel
[i].EnabledForActivity = 1;
in fiji_populate_smc_link_level()
842
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in fiji_populate_smc_link_level()
843
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in fiji_populate_smc_link_level()
844
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in fiji_populate_smc_link_level()
H
A
D
iceland_smumgr.c
773
table->
LinkLevel
[i].PcieGenSpeed =
in iceland_populate_smc_link_level()
775
table->
LinkLevel
[i].PcieLaneCount =
in iceland_populate_smc_link_level()
777
table->
LinkLevel
[i].EnabledForActivity =
in iceland_populate_smc_link_level()
779
table->
LinkLevel
[i].SPC =
in iceland_populate_smc_link_level()
781
table->
LinkLevel
[i].DownThreshold =
in iceland_populate_smc_link_level()
783
table->
LinkLevel
[i].UpThreshold =
in iceland_populate_smc_link_level()
H
A
D
polaris10_smumgr.c
826
table->
LinkLevel
[i].PcieGenSpeed =
in polaris10_populate_smc_link_level()
828
table->
LinkLevel
[i].PcieLaneCount = (uint8_t)encode_pcie_lane_width(
in polaris10_populate_smc_link_level()
830
table->
LinkLevel
[i].EnabledForActivity = 1;
in polaris10_populate_smc_link_level()
831
table->
LinkLevel
[i].SPC = (uint8_t)(data->pcie_spc_cap & 0xff);
in polaris10_populate_smc_link_level()
832
table->
LinkLevel
[i].DownThreshold = PP_HOST_TO_SMC_UL(5);
in polaris10_populate_smc_link_level()
833
table->
LinkLevel
[i].UpThreshold = PP_HOST_TO_SMC_UL(30);
in polaris10_populate_smc_link_level()
2100
table->
LinkLevel
[i-1].BifSclkDfs = PP_HOST_TO_SMC_US((USHORT)(dividers.pll_post_divider));
in polaris10_init_smc_table()
H
A
D
tonga_smumgr.c
516
table->
LinkLevel
[i].PcieGenSpeed =
in tonga_populate_smc_link_level()
518
table->
LinkLevel
[i].PcieLaneCount =
in tonga_populate_smc_link_level()
520
table->
LinkLevel
[i].EnabledForActivity =
in tonga_populate_smc_link_level()
522
table->
LinkLevel
[i].SPC =
in tonga_populate_smc_link_level()
524
table->
LinkLevel
[i].DownThreshold =
in tonga_populate_smc_link_level()
526
table->
LinkLevel
[i].UpThreshold =
in tonga_populate_smc_link_level()
H
A
D
ci_smumgr.c
1006
table->
LinkLevel
[i].PcieGenSpeed =
in ci_populate_smc_link_level()
1008
table->
LinkLevel
[i].PcieLaneCount =
in ci_populate_smc_link_level()
1010
table->
LinkLevel
[i].EnabledForActivity = 1;
in ci_populate_smc_link_level()
1011
table->
LinkLevel
[i].DownT = PP_HOST_TO_SMC_UL(5);
in ci_populate_smc_link_level()
1012
table->
LinkLevel
[i].UpT = PP_HOST_TO_SMC_UL(30);
in ci_populate_smc_link_level()
/kernel/linux/linux-5.10/drivers/gpu/drm/amd/pm/inc/
H
A
D
smu7_discrete.h
326
SMU7_Discrete_LinkLevel
LinkLevel
[SMU7_MAX_LEVELS_LINK];
member
H
A
D
smu71_discrete.h
273
SMU71_Discrete_LinkLevel
LinkLevel
[SMU71_MAX_LEVELS_LINK];
member
H
A
D
smu75_discrete.h
290
SMU75_Discrete_LinkLevel
LinkLevel
[SMU75_MAX_LEVELS_LINK];
member
H
A
D
smu74_discrete.h
284
SMU74_Discrete_LinkLevel
LinkLevel
[SMU74_MAX_LEVELS_LINK];
member
H
A
D
smu72_discrete.h
268
SMU72_Discrete_LinkLevel
LinkLevel
[SMU72_MAX_LEVELS_LINK];
member
H
A
D
smu73_discrete.h
252
SMU73_Discrete_LinkLevel
LinkLevel
[SMU73_MAX_LEVELS_LINK];
member
/kernel/linux/linux-5.10/drivers/gpu/drm/radeon/
H
A
D
smu7_discrete.h
325
SMU7_Discrete_LinkLevel
LinkLevel
[SMU7_MAX_LEVELS_LINK];
member
/kernel/linux/linux-6.6/drivers/gpu/drm/amd/pm/powerplay/inc/
H
A
D
smu71_discrete.h
273
SMU71_Discrete_LinkLevel
LinkLevel
[SMU71_MAX_LEVELS_LINK];
member
H
A
D
smu7_discrete.h
326
SMU7_Discrete_LinkLevel
LinkLevel
[SMU7_MAX_LEVELS_LINK];
member
H
A
D
smu75_discrete.h
290
SMU75_Discrete_LinkLevel
LinkLevel
[SMU75_MAX_LEVELS_LINK];
member
H
A
D
smu74_discrete.h
285
SMU74_Discrete_LinkLevel
LinkLevel
[SMU74_MAX_LEVELS_LINK];
member
H
A
D
smu72_discrete.h
268
SMU72_Discrete_LinkLevel
LinkLevel
[SMU72_MAX_LEVELS_LINK];
member
/kernel/linux/linux-6.6/drivers/gpu/drm/radeon/
H
A
D
smu7_discrete.h
325
SMU7_Discrete_LinkLevel
LinkLevel
[SMU7_MAX_LEVELS_LINK];
member
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