LANE_PLL_ENABLE (reference) in projects: kernel - OpenGrok search results

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Searched refs:LANE_PLL_ENABLE (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/gma500/
H A D	cdv_intel_display.c	`338 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 344 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 350 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 356 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()`
H A D	psb_intel_reg.h	`1369 #define LANE_PLL_ENABLE (0x3 << 20) macro`
/kernel/linux/linux-6.6/drivers/gpu/drm/gma500/
H A D	cdv_intel_display.c	`339 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 345 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 351 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv() 357 lane_value \|= LANE_PLL_ENABLE \| LANE_PLL_PIPE(pipe); in cdv_dpll_set_clock_cdv()`
H A D	psb_intel_reg.h	`1327 #define LANE_PLL_ENABLE (0x3 << 20) macro`

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