Home
last modified time | relevance | path

Searched refs:INTEN0 (Results 1 - 4 of 4) sorted by relevance

/kernel/linux/linux-5.10/drivers/net/ethernet/amd/
H A Damd8111e.c383 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
397 writel(VAL0|STINTEN,mmio+INTEN0); in amd8111e_set_coalesce()
404 writel(STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
411 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
448 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); in amd8111e_restart()
450 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_restart()
544 /* Clear INTEN0 */ in amd8111e_init_hw_default()
545 writel( INTEN0_CLEAR, mmio + INTEN0); in amd8111e_init_hw_default()
784 writel(VAL0|RINTEN0, mmio + INTEN0); in amd8111e_rx_poll()
1104 intren0 = readl(mmio + INTEN0); in amd8111e_interrupt()
[all...]
H A Damd8111e.h30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
45 #define INTEN0 0x40 /* Interrupt0 enable register*/ macro
/kernel/linux/linux-6.6/drivers/net/ethernet/amd/
H A Damd8111e.c382 writel(VAL0|STINTEN, mmio+INTEN0); in amd8111e_set_coalesce()
396 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()
403 writel(STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()
410 writel(VAL0 | STINTEN, mmio + INTEN0); in amd8111e_set_coalesce()
447 SPNDINTEN | MPINTEN | SINTEN | STINTEN, mmio + INTEN0); in amd8111e_restart()
449 writel(VAL3 | LCINTEN | VAL1 | TINTEN0 | VAL0 | RINTEN0, mmio + INTEN0); in amd8111e_restart()
543 /* Clear INTEN0 */ in amd8111e_init_hw_default()
544 writel(INTEN0_CLEAR, mmio + INTEN0); in amd8111e_init_hw_default()
783 writel(VAL0|RINTEN0, mmio + INTEN0); in amd8111e_rx_poll()
1096 intren0 = readl(mmio + INTEN0); in amd8111e_interrupt()
[all...]
H A Damd8111e.h30 Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the value bit that specifies the value that will be written into the selected bits of register.
45 #define INTEN0 0x40 /* Interrupt0 enable register*/ macro

Completed in 8 milliseconds