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Searched refs:IMX6SL_CLK_PLL4_POST_DIV (Results 1 - 6 of 6) sorted by relevance

/kernel/linux/linux-5.10/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx6sl-clock.h23 #define IMX6SL_CLK_PLL4_POST_DIV 14 macro
/kernel/linux/linux-5.10/include/dt-bindings/clock/
H A Dimx6sl-clock.h23 #define IMX6SL_CLK_PLL4_POST_DIV 14 macro
/kernel/linux/linux-6.6/include/dt-bindings/clock/
H A Dimx6sl-clock.h23 #define IMX6SL_CLK_PLL4_POST_DIV 14 macro
/kernel/linux/linux-6.6/scripts/dtc/include-prefixes/dt-bindings/clock/
H A Dimx6sl-clock.h23 #define IMX6SL_CLK_PLL4_POST_DIV 14 macro
/kernel/linux/linux-5.10/drivers/clk/imx/
H A Dclk-imx6sl.c266 hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sl_clocks_init()
/kernel/linux/linux-6.6/drivers/clk/imx/
H A Dclk-imx6sl.c267 hws[IMX6SL_CLK_PLL4_POST_DIV] = clk_hw_register_divider_table(NULL, "pll4_post_div", "pll4_audio", CLK_SET_RATE_PARENT, base + 0x70, 19, 2, 0, post_div_table, &imx_ccm_lock); in imx6sl_clocks_init()

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