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Searched refs:HVS_READ (Results 1 - 8 of 8) sorted by relevance

/kernel/linux/linux-5.10/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c217 reg = HVS_READ(SCALER_DISPECTRL); in vc4_hvs_get_fifo_from_output()
225 reg = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_get_fifo_from_output()
233 reg = HVS_READ(SCALER_DISPEOLN); in vc4_hvs_get_fifo_from_output()
241 reg = HVS_READ(SCALER_DISPDITHER); in vc4_hvs_get_fifo_from_output()
288 dispbkgndx = HVS_READ(SCALER_DISPBKGNDX(chan)); in vc4_hvs_init_channel()
309 if (HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_ENABLE) in vc4_hvs_stop_channel()
313 HVS_READ(SCALER_DISPCTRLX(chan)) | SCALER_DISPCTRLX_RESET); in vc4_hvs_stop_channel()
315 HVS_READ(SCALER_DISPCTRLX(chan)) & ~SCALER_DISPCTRLX_ENABLE); in vc4_hvs_stop_channel()
318 WARN_ON_ONCE(HVS_READ(SCALER_DISPCTRLX(chan)) & SCALER_DISPCTRLX_RESET); in vc4_hvs_stop_channel()
320 WARN_ON_ONCE(VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT in vc4_hvs_stop_channel()
[all...]
H A Dvc4_kms.c231 dispctrl = HVS_READ(SCALER_DISPCTRL) & in vc4_hvs_pv_muxing_commit()
256 reg = HVS_READ(SCALER_DISPECTRL); in vc5_hvs_pv_muxing_commit()
268 reg = HVS_READ(SCALER_DISPCTRL); in vc5_hvs_pv_muxing_commit()
280 reg = HVS_READ(SCALER_DISPEOLN); in vc5_hvs_pv_muxing_commit()
293 reg = HVS_READ(SCALER_DISPDITHER); in vc5_hvs_pv_muxing_commit()
H A Dvc4_crtc.c71 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); in vc4_crtc_get_cob_allocation()
108 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); in vc4_crtc_get_scanout_position()
421 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != in require_hvs_enabled()
654 (vc4_state->mm.start == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
H A Dvc4_drv.h549 #define HVS_READ(offset) readl(vc4->hvs->regs + offset) macro
/kernel/linux/linux-6.6/drivers/gpu/drm/vc4/
H A Dvc4_hvs.c118 dispstat = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTATX(i)), in vc4_hvs_debugfs_dlist()
128 for (j = HVS_READ(SCALER_DISPLISTX(i)); j < 256; j++) { in vc4_hvs_debugfs_dlist()
271 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
275 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT1), in vc4_hvs_get_fifo_frame_count()
279 field = VC4_GET_FIELD(HVS_READ(SCALER_DISPSTAT2), in vc4_hvs_get_fifo_frame_count()
311 reg = HVS_READ(SCALER_DISPECTRL); in vc4_hvs_get_fifo_from_output()
319 reg = HVS_READ(SCALER_DISPCTRL); in vc4_hvs_get_fifo_from_output()
327 reg = HVS_READ(SCALER_DISPEOLN); in vc4_hvs_get_fifo_from_output()
335 reg = HVS_READ(SCALER_DISPDITHER); in vc4_hvs_get_fifo_from_output()
373 dispbkgndx = HVS_READ(SCALER_DISPBKGND in vc4_hvs_init_channel()
[all...]
H A Dvc4_kms.c243 dispctrl = HVS_READ(SCALER_DISPCTRL) & in vc4_hvs_pv_muxing_commit()
270 VC4_GET_FIELD(HVS_READ(SCALER_DISPCTRL), in vc5_hvs_pv_muxing_commit()
274 reg = HVS_READ(SCALER_DISPECTRL); in vc5_hvs_pv_muxing_commit()
286 reg = HVS_READ(SCALER_DISPCTRL); in vc5_hvs_pv_muxing_commit()
298 reg = HVS_READ(SCALER_DISPEOLN); in vc5_hvs_pv_muxing_commit()
311 reg = HVS_READ(SCALER_DISPDITHER); in vc5_hvs_pv_muxing_commit()
H A Dvc4_crtc.c86 u32 dispbase = HVS_READ(SCALER_DISPBASEX(channel)); in vc4_crtc_get_cob_allocation()
124 val = HVS_READ(SCALER_DISPSTATX(vc4_crtc_state->assigned_channel)); in vc4_crtc_get_scanout_position()
461 WARN_ON_ONCE((HVS_READ(SCALER_DISPCTRL) & SCALER_DISPCTRL_ENABLE) != in require_hvs_enabled()
790 (vc4_crtc->current_dlist == HVS_READ(SCALER_DISPLACTX(chan)) || in vc4_crtc_handle_page_flip()
H A Dvc4_drv.h630 #define HVS_READ(offset) \ macro

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