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Searched
refs:GIC_REG_32
(Results
1 - 3
of
3
) sorted by relevance
/kernel/liteos_a/arch/arm/gic/
H
A
D
gic_v3.c
140
while (
GIC_REG_32
(reg) & GICD_CTLR_RWP) {
in GicWaitForRwp()
143
PRINTK("gic_v3: rwp timeout 0x%x\n",
GIC_REG_32
(reg));
in GicWaitForRwp()
153
GIC_REG_32
(GICD_IGROUPR(irq / 32)) = 0; /* 32: Interrupt bit width */
in GicdSetGroup()
155
GIC_REG_32
(GICD_IGROUPR(irq / 32)) = 0xffffffff; /* 32: Interrupt bit width */
in GicdSetGroup()
161
GIC_REG_32
(GICR_WAKER(cpu)) &= ~GICR_WAKER_PROCESSORSLEEP;
in GicrSetWaker()
164
while ((
GIC_REG_32
(GICR_WAKER(cpu)) & 0x4) == GICR_WAKER_CHILDRENASLEEP);
in GicrSetWaker()
171
GIC_REG_32
(GICR_IGROUPR0(cpu)) = 0;
in GicrSetGroup()
172
GIC_REG_32
(GICR_IGRPMOD0(cpu)) = 0;
in GicrSetGroup()
174
GIC_REG_32
(GICR_IGROUPR0(cpu)) = 0xffffffff;
in GicrSetGroup()
181
UINT32 newPri =
GIC_REG_32
(GICD_IPRIORITY
in GicdSetPmr()
[all...]
H
A
D
gic_v2.c
55
GIC_REG_32
(GICD_SGIR) = val;
in GicWriteSgi()
83
GIC_REG_32
(GICD_ICENABLER(vector / 32)) = 1U << (vector % 32); /* 32: Interrupt bit width */
in HalIrqMask()
92
GIC_REG_32
(GICD_ISENABLER(vector >> 5)) = 1U << (vector % 32); /* 5, 32: Register bit offset */
in HalIrqUnmask()
101
GIC_REG_32
(GICD_ISPENDR(vector >> 5)) = 1U << (vector % 32); /* 5, 32: Register bit offset */
in HalIrqPending()
106
GIC_REG_32
(GICC_EOIR) = vector;
in HalIrqClear()
112
GIC_REG_32
(GICC_PMR) = 0xFF;
in HalIrqInitPercpu()
115
GIC_REG_32
(GICC_CTLR) = 1;
in HalIrqInitPercpu()
124
GIC_REG_32
(GICD_ICFGR(i / 16)) = 0; /* 16: Register bit offset */
in HalIrqInit()
129
GIC_REG_32
(GICD_ITARGETSR(i / 4)) = 0x01010101;
in HalIrqInit()
134
GIC_REG_32
(GICD_IPRIORITY
in HalIrqInit()
[all...]
/kernel/liteos_a/arch/arm/include/
H
A
D
gic_common.h
85
#define
GIC_REG_32
(reg) (*(volatile UINT32 *)((UINTPTR)(GIC_BASE_ADDR + (reg))))
macro
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