Searched refs:GICD_ICFGR (Results 1 - 11 of 11) sorted by relevance
| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/include/aarch64/ |
| H A D | gic_v3.h | 24 #define GICD_ICFGR 0x0C00 macro
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| /kernel/liteos_a/arch/arm/include/ |
| H A D | gic_common.h | 72 #define GICD_ICFGR(n) (GICD_OFFSET + 0xc00 + (n) * 4) /* Interrupt Configuration Registers */ macro
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| /kernel/liteos_a/arch/arm/gic/ |
| H A D | gic_v2.c | 124 GIC_REG_32(GICD_ICFGR(i / 16)) = 0; /* 16: Register bit offset */ in HalIrqInit()
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| H A D | gic_v3.c | 367 GIC_REG_32(GICD_ICFGR(i / 16)) = 0; in HalIrqInit()
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| /kernel/linux/linux-5.10/include/linux/irqchip/ |
| H A D | arm-gic-v3.h | 30 #define GICD_ICFGR 0x0C00 macro
236 #define GICR_ICFGR0 GICD_ICFGR
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| /kernel/linux/linux-6.6/include/linux/irqchip/ |
| H A D | arm-gic-v3.h | 30 #define GICD_ICFGR 0x0C00 macro
238 #define GICR_ICFGR0 GICD_ICFGR
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| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/lib/aarch64/ |
| H A D | gic_v3.c | 215 gicv3_write_reg(intid, GICD_ICFGR, 32, 2, val); in gicv3_irq_set_config()
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| /kernel/linux/linux-5.10/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio-v3.c | 595 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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| /kernel/linux/linux-6.6/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio-v3.c | 660 REGISTER_DESC_WITH_BITS_PER_IRQ_SHARED(GICD_ICFGR,
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| /kernel/linux/linux-5.10/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 321 case GICD_ICFGR: in convert_offset_index()
597 offset = convert_offset_index(d, GICD_ICFGR, &index); in gic_set_type()
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| /kernel/linux/linux-6.6/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 357 case GICD_ICFGR: in convert_offset_index()
671 offset = convert_offset_index(d, GICD_ICFGR, &index); in gic_set_type()
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