Searched refs:GICD_CTLR (Results 1 - 11 of 11) sorted by relevance
| /kernel/liteos_a/arch/arm/gic/ |
| H A D | gic_v3.c | 264 GicWaitForRwp(GICD_CTLR); in HalIrqMask()
284 GicWaitForRwp(GICD_CTLR); in HalIrqUnmask()
361 GIC_REG_32(GICD_CTLR) = 0; in HalIrqInit()
362 GicWaitForRwp(GICD_CTLR); in HalIrqInit()
384 GicWaitForRwp(GICD_CTLR); in HalIrqInit()
392 GIC_REG_32(GICD_CTLR) = CTLR_ENALBE_G0 | CTLR_ENABLE_G1NS | CTLR_ARE_S; in HalIrqInit()
|
| H A D | gic_v2.c | 145 GIC_REG_32(GICD_CTLR) = 1; in HalIrqInit()
|
| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/lib/aarch64/ |
| H A D | gic_v3.c | 38 while (readl(gicv3_data.dist_base + GICD_CTLR) & GICD_CTLR_RWP) { in gicv3_gicd_wait_for_rwp()
334 writel(0, dist_base + GICD_CTLR); in gicv3_dist_init()
357 GICD_CTLR_ENABLE_G1, dist_base + GICD_CTLR); in gicv3_dist_init()
|
| /kernel/linux/linux-6.6/tools/testing/selftests/kvm/include/aarch64/ |
| H A D | gic_v3.h | 14 #define GICD_CTLR 0x0000 macro
28 * The following bits of GICD_CTLR are defined accordingly.
|
| /kernel/liteos_a/arch/arm/include/ |
| H A D | gic_common.h | 60 #define GICD_CTLR (GICD_OFFSET + 0x000) /* Distributor Control Register */ macro
|
| /kernel/linux/linux-5.10/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio-v3.c | 71 case GICD_CTLR: in vgic_mmio_read_v3_misc()
111 case GICD_CTLR: { in vgic_mmio_write_v3_misc()
165 case GICD_CTLR: in vgic_mmio_uaccess_write_v3_misc()
555 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
|
| /kernel/linux/linux-6.6/arch/arm64/kvm/vgic/ |
| H A D | vgic-mmio-v3.c | 71 case GICD_CTLR: in vgic_mmio_read_v3_misc()
111 case GICD_CTLR: { in vgic_mmio_write_v3_misc()
179 case GICD_CTLR: in vgic_mmio_uaccess_write_v3_misc()
620 REGISTER_DESC_WITH_LENGTH_UACCESS(GICD_CTLR,
|
| /kernel/linux/linux-5.10/include/linux/irqchip/ |
| H A D | arm-gic-v3.h | 13 #define GICD_CTLR 0x0000 macro
114 #define GICR_CTLR GICD_CTLR
|
| /kernel/linux/linux-6.6/include/linux/irqchip/ |
| H A D | arm-gic-v3.h | 13 #define GICD_CTLR 0x0000 macro
114 #define GICR_CTLR GICD_CTLR
|
| /kernel/linux/linux-5.10/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 109 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
214 while (readl_relaxed(base + GICD_CTLR) & bit) { in gic_do_wait_for_rwp()
779 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init()
816 writel_relaxed(val, base + GICD_CTLR); in gic_dist_init()
972 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; in gic_dist_security_disabled()
|
| /kernel/linux/linux-6.6/drivers/irqchip/ |
| H A D | irq-gic-v3.c | 112 * When GIC security is enabled (GICD_CTLR.DS == 0), the interrupt priority
250 while (readl_relaxed(base + GICD_CTLR) & bit) { in gic_do_wait_for_rwp()
915 writel_relaxed(0, base + GICD_CTLR); in gic_dist_init()
952 writel_relaxed(val, base + GICD_CTLR); in gic_dist_init()
1125 return readl_relaxed(gic_data.dist_base + GICD_CTLR) & GICD_CTLR_DS; in gic_dist_security_disabled()
|
Completed in 15 milliseconds