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Searched refs:GEN8_MASTER_IRQ (Results 1 - 10 of 10) sorted by relevance

/kernel/linux/linux-6.6/drivers/gpu/drm/i915/
H A Di915_irq.c354 master_ctl = intel_uncore_read(&dev_priv->uncore, GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
366 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && in cherryview_irq_handler()
367 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); in cherryview_irq_handler()
375 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
400 intel_uncore_write(&dev_priv->uncore, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
495 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
503 return raw_reg_read(regs, GEN8_MASTER_IRQ); in gen8_master_intr_disable()
508 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
760 intel_uncore_write(uncore, GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
761 intel_uncore_posting_read(&dev_priv->uncore, GEN8_MASTER_IRQ); in cherryview_irq_reset()
[all...]
H A Dintel_gvt_mmio_table.c769 MMIO_D(GEN8_MASTER_IRQ); in iterate_bdw_plus_mmio()
H A Di915_reg.h4325 #define GEN8_MASTER_IRQ _MMIO(0x44200) macro
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c217 * GEN8_MASTER_IRQ is a special irq register, in intel_vgpu_reg_master_irq_handler()
459 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
473 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
490 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
H A Dhandlers.c2816 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/kernel/linux/linux-6.6/drivers/gpu/drm/i915/gvt/
H A Dinterrupt.c220 * GEN8_MASTER_IRQ is a special irq register, in intel_vgpu_reg_master_irq_handler()
498 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
512 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
529 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
H A Dhandlers.c2495 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, in init_bdw_mmio_info()
/kernel/linux/linux-5.10/drivers/gpu/drm/i915/
H A Di915_irq.c1624 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
1636 * ((GEN8_MASTER_IRQ & ~GEN8_MASTER_IRQ_CONTROL) && in cherryview_irq_handler()
1637 * (GEN8_MASTER_IRQ & GEN8_MASTER_IRQ_CONTROL))); in cherryview_irq_handler()
1645 I915_WRITE(GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
1671 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
2379 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
2387 return raw_reg_read(regs, GEN8_MASTER_IRQ); in gen8_master_intr_disable()
2392 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
2474 * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ in gen11_display_irq_handler()
2964 I915_WRITE(GEN8_MASTER_IRQ, in cherryview_irq_reset()
[all...]
H A Di915_debugfs.c446 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
526 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
H A Di915_reg.h7621 #define GEN8_MASTER_IRQ _MMIO(0x44200) macro

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